Quantum Computing and Semiconductor Technology covers the intersection of quantum computing hardware and semiconductor fabrication — specifically, how advanced CMOS processes are used to fabricate superconducting qubits, silicon spin qubits, and the classical cryo-CMOS control electronics that interface with quantum processors, positioning semiconductor fabs as enablers of scalable quantum computing.

Qubit Technologies and Semiconductor Relevance:

Superconducting Qubit Fabrication:

Typical transmon qubit process:
1. Silicon substrate (high-resistivity >10 kΩ·cm)
2. Nb or Al deposition (sputtering or e-beam evaporation)
3. Patterning of capacitor pads and resonators (optical litho or e-beam)
4. Josephson junction: Dolan bridge or bridge-free technique
   - Angle evaporation: Al (first layer) → Oxidize → Al (second layer)
   - Creates Al/AlOx/Al tunnel junction (~100nm × 100nm)
5. Etch isolation and release
6. Test at mK temperatures in dilution refrigerator

Fabrication is relatively simple (~5-10 lithography steps) compared to CMOS (~60-100+ steps), but material quality is paramount: two-level system (TLS) defects in surface oxides, substrate interfaces, and junction barriers limit qubit coherence times. Sub-ppb metallic contamination and surface chemistry control are critical.

Silicon Spin Qubits (CMOS Qubits):

The most CMOS-compatible approach — quantum dots formed in silicon MOS structures:

Silicon spin qubit device:
  Si/SiGe heterostructure or Si-MOS
  Gate electrodes (~20-50nm pitch) define quantum dots
  Each dot traps 1-2 electrons
  Qubit = spin state (up/down) of trapped electron
  Control: microwave pulses + gate voltage manipulation
  Readout: spin-to-charge conversion + charge sensor

Advantage: Potentially fabricable in existing CMOS fabs
  Intel fabricates spin qubits on 300mm wafers (Intel Tunnel Falls)
  IMEC developing SiGe quantum dot arrays on 300mm

Cryo-CMOS Control Electronics:

Quantum processors require classical electronics for qubit control, readout, and error correction. Placing these at cryogenic temperatures (4K stage of dilution refrigerator) reduces wiring complexity:

Room temperature: Digital control systems, DACs, ADCs
  ↕ Thousands of coax lines (current approach)
4K stage: Cryo-CMOS multiplexers, amplifiers
  ↕ Fewer wires needed (multiplexed)
100mK-15mK stage: Qubit chip

Cryo-CMOS challenges:
  - MOSFET behavior changes at 4K (threshold voltage shift, kink effect)
  - Standard SPICE models invalid below ~77K
  - Power dissipation must be ultra-low (<10mW at 4K)
  - Process qualification at cryogenic temperatures

Intel, TSMC, and GlobalFoundries are developing cryo-CMOS processes. Intel's Horse Ridge II is a cryo-CMOS controller chip fabricated in 22nm FinFET operating at 4K.

Scaling Challenges:

• Wiring bottleneck: 1000 qubits × 2-3 control lines each = 3000+ coax cables from room temp to mK. Cryo-CMOS multiplexing is essential.
• Qubit uniformity: Quantum error correction requires uniform qubits (same frequency, coherence). Fab process variation causes qubit-to-qubit variability.
• Yield: A 1000-qubit chip with 99% per-qubit yield has only 0.99^1000 ≈ 0.004% probability of all qubits working. Redundancy and calibration are essential.

Semiconductor fabrication technology is the manufacturing foundation for scalable quantum computing — whether through superconducting circuits, silicon spin qubits, or cryo-CMOS control chips, the path to fault-tolerant quantum computers depends critically on the precision, uniformity, and scalability that only semiconductor fabs can provide.