RC Delay Overview

RC delay is the signal propagation delay through interconnect wires caused by the resistance (R) of the metal conductor and the capacitance (C) between adjacent wires and layers. At advanced nodes, RC delay dominates over transistor gate delay.

Why RC Delay Matters

• At 180nm+: Gate delay > wire delay. Transistor speed was the bottleneck.
• At 90nm and below: Wire delay > gate delay. Interconnect RC now limits chip performance.
• Scaling makes it worse: Thinner, narrower wires → higher R. Closer spacing → higher C.

Delay Formula

RC delay ∝ R × C = (ρ × L) / (W × T) × (ε × L × T) / S Where: ρ = resistivity, L = wire length, W = width, T = thickness, ε = dielectric constant, S = spacing.

Reduction Strategies

• Lower R (resistance):
• Copper replaced aluminum (ρ: 1.7 vs. 2.7 μΩ·cm).
• Ruthenium and molybdenum explored for ultra-narrow wires (better resistivity scaling than Cu at < 15nm width).
• Wider/taller wires on upper metal layers for global signals.
• Lower C (capacitance):
• Low-k dielectrics (k = 2.5-3.0) replaced SiO₂ (k = 3.9-4.2).
• Ultra-low-k (ULK, k = 2.0-2.5) with porosity for most advanced nodes.
• Air-gap integration (k ≈ 1.0) between critical metal lines.
• Architecture:
• Repeater/buffer insertion breaks long RC paths.
• Wire length minimization through better place-and-route algorithms.
• More metal layers spread routing across levels, reducing individual wire lengths.