<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 760 470" font-family="Segoe UI,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">RDL: copper-on-polymer routing that re-pitches die I/O to the board</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Thin-film copper in spin-coated polymer re-routes fine die pads to coarse ball pitch — fanning I/O past the die edge</text><!-- ===== PANEL 1 ===== --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="36" y="92" fill="#38bdf8" font-size="14" font-weight="700">1 · Pitch translation</text><!-- die + fine pads --><rect x="66" y="108" width="120" height="24" rx="3" fill="#1c2733" stroke="#6f8fb0"/><text x="126" y="124" text-anchor="middle" fill="#adb5bd" font-size="9.5">die — fine pads</text><g fill="#b8732e"><circle cx="72" cy="137" r="2"/><circle cx="82" cy="137" r="2"/><circle cx="92" cy="137" r="2"/><circle cx="102" cy="137" r="2"/><circle cx="112" cy="137" r="2"/><circle cx="122" cy="137" r="2"/><circle cx="132" cy="137" r="2"/><circle cx="142" cy="137" r="2"/><circle cx="152" cy="137" r="2"/><circle cx="162" cy="137" r="2"/><circle cx="172" cy="137" r="2"/><circle cx="182" cy="137" r="2"/></g><!-- RDL region with fan traces --><rect x="38" y="144" width="186" height="36" rx="2" fill="#14202b" stroke="#30363d"/><text x="131" y="165" text-anchor="middle" fill="#586b7a" font-size="8.5">RDL</text><g stroke="#b8732e" stroke-width="1.3" fill="none"><line x1="77" y1="144" x2="52" y2="180"/><line x1="97" y1="144" x2="82" y2="180"/><line x1="117" y1="144" x2="110" y2="180"/><line x1="137" y1="144" x2="140" y2="180"/><line x1="160" y1="144" x2="170" y2="180"/><line x1="180" y1="144" x2="200" y2="180"/></g><!-- coarse balls --><g fill="#e0b13a"><circle cx="52" cy="185" r="4"/><circle cx="82" cy="185" r="4"/><circle cx="110" cy="185" r="4"/><circle cx="140" cy="185" r="4"/><circle cx="170" cy="185" r="4"/><circle cx="200" cy="185" r="4"/></g><text x="126" y="202" text-anchor="middle" fill="#8b949e" font-size="8.5">coarse ball pitch</text><text x="36" y="224" fill="#adb5bd" font-size="11">RDL turns tight die-pad pitch into</text><text x="36" y="239" fill="#adb5bd" font-size="11">board-friendly ball pitch —</text><text x="36" y="264" fill="#38bdf8" font-size="11" font-weight="700">and fans I/O past the die edge.</text><text x="36" y="289" fill="#8b949e" font-size="10.5">~10–40 µm pads in →</text><text x="36" y="304" fill="#8b949e" font-size="10.5">~100–500 µm balls out.</text><text x="36" y="329" fill="#8b949e" font-size="10.5">The enabling interconnect for</text><text x="36" y="343" fill="#8b949e" font-size="10.5">WLCSP, fan-out and chiplets.</text><!-- ===== PANEL 2 ===== --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="283" y="92" fill="#38bdf8" font-size="14" font-weight="700">2 · The copper/polymer stack</text><text x="330" y="110" fill="#adb5bd" font-size="8">die pad</text><rect x="312" y="112" width="14" height="8" fill="#b8732e"/><!-- polymer block --><rect x="300" y="118" width="140" height="80" rx="2" fill="#241a12" stroke="#5a4632"/><!-- M1 --><rect x="308" y="132" width="66" height="6" fill="#b8732e"/><text x="310" y="130" fill="#f0d9b5" font-size="8">M1</text><rect x="368" y="132" width="6" height="20" fill="#d08a4a"/><!-- M2 --><rect x="360" y="150" width="66" height="6" fill="#b8732e"/><text x="362" y="148" fill="#f0d9b5" font-size="8">M2</text><rect x="418" y="150" width="6" height="22" fill="#d08a4a"/><!-- M3 --><rect x="336" y="170" width="88" height="6" fill="#b8732e"/><text x="338" y="168" fill="#f0d9b5" font-size="8">M3</text><rect x="360" y="176" width="6" height="18" fill="#d08a4a"/><text x="384" y="146" fill="#9fd8ef" font-size="8">via</text><!-- UBM + ball --><rect x="354" y="192" width="18" height="5" fill="#586069"/><circle cx="363" cy="203" r="6" fill="#e0b13a"/><text x="376" y="206" fill="#adb5bd" font-size="8">UBM + ball</text><text x="283" y="226" fill="#c9d1d9" font-size="10.5">3–4 copper layers in polymer;</text><text x="283" y="241" fill="#c9d1d9" font-size="10.5">vias step signals between them.</text><text x="283" y="264" fill="#c4b5fd" font-size="10.5">PI: Dk ~3.5   ·   PBO: Dk ~2.6</text><text x="283" y="285" fill="#adb5bd" font-size="10.5">Line/space scales from</text><text x="283" y="300" fill="#adb5bd" font-size="10.5">10/10 µm down to 2/2 µm.</text><text x="283" y="325" fill="#8b949e" font-size="10.5">Finer L/S → more routing per</text><text x="283" y="339" fill="#8b949e" font-size="10.5">layer, but harder to yield.</text><!-- ===== PANEL 3 ===== --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="530" y="92" fill="#38bdf8" font-size="14" font-weight="700">3 · Building it &amp; the knobs</text><g font-size="9.5" font-weight="700" fill="#0d1117"><circle cx="537" cy="112" r="6.5" fill="#38bdf8"/><text x="537" y="115" text-anchor="middle">1</text><circle cx="537" cy="132" r="6.5" fill="#38bdf8"/><text x="537" y="135" text-anchor="middle">2</text><circle cx="537" cy="152" r="6.5" fill="#38bdf8"/><text x="537" y="155" text-anchor="middle">3</text><circle cx="537" cy="172" r="6.5" fill="#38bdf8"/><text x="537" y="175" text-anchor="middle">4</text><circle cx="537" cy="192" r="6.5" fill="#38bdf8"/><text x="537" y="195" text-anchor="middle">5</text></g><text x="549" y="115" fill="#c9d1d9" font-size="10">Spin-coat polymer, bake, cure</text><text x="549" y="135" fill="#c9d1d9" font-size="10">Open vias — laser or litho</text><text x="549" y="155" fill="#c9d1d9" font-size="10">Sputter a copper seed layer</text><text x="549" y="175" fill="#c9d1d9" font-size="10">Electroplate Cu, pattern, etch</text><text x="549" y="195" fill="#c9d1d9" font-size="10">Repeat per layer (2–8 layers)</text><line x1="530" y1="208" x2="724" y2="208" stroke="#30363d"/><text x="530" y="228" fill="#e0b13a" font-size="11.5" font-weight="700">The hard parts</text><g fill="#e0b13a"><circle cx="534" cy="241" r="2.6"/><circle cx="534" cy="256" r="2.6"/><circle cx="534" cy="271" r="2.6"/><circle cx="534" cy="286" r="2.6"/></g><text x="544" y="244" fill="#adb5bd" font-size="10.5">layer-to-layer overlay/alignment</text><text x="544" y="259" fill="#adb5bd" font-size="10.5">fine L/S yield (down to 2/2 µm)</text><text x="544" y="274" fill="#adb5bd" font-size="10.5">copper plating uniformity</text><text x="544" y="289" fill="#adb5bd" font-size="10.5">polymer-cure stress → warpage</text><text x="530" y="315" fill="#f87171" font-size="10.5" font-weight="700">Overlay and plating set how tight</text><text x="530" y="329" fill="#f87171" font-size="10.5" font-weight="700">the RDL can be pushed.</text><!-- ===== BOTTOM CARDS ===== --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="36" y="406" fill="#38bdf8" font-size="12.5" font-weight="700">Pitch translator</text><text x="36" y="424" fill="#adb5bd" font-size="10">Converts µm-pitch die bumps into</text><text x="36" y="437" fill="#adb5bd" font-size="10">board-friendly ball pitch and fans</text><text x="36" y="450" fill="#adb5bd" font-size="10">I/O past the die edge.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="283" y="406" fill="#c4b5fd" font-size="12.5" font-weight="700">Copper on polymer</text><text x="283" y="424" fill="#adb5bd" font-size="10">Plated copper traces sit in spin-</text><text x="283" y="437" fill="#adb5bd" font-size="10">coated PI/PBO; stack 2–8 layers</text><text x="283" y="450" fill="#adb5bd" font-size="10">with vias between them.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="530" y="406" fill="#e0b13a" font-size="12.5" font-weight="700">Alignment &amp; plating gate yield</text><text x="530" y="424" fill="#adb5bd" font-size="10">Layer overlay, fine line/space and</text><text x="530" y="437" fill="#adb5bd" font-size="10">copper plating uniformity set how</text><text x="530" y="450" fill="#adb5bd" font-size="10">tight RDL can go.</text></svg>

Redistribution Layer RDL Process is a interconnect metallization technology creating flexible routing patterns converting high-density die-level bump pitches to larger substrate-level spacing, enabling heterogeneous die integration and fan-out packaging — essential for advanced chiplet and heterogeneous integration.

RDL Function and Architecture

Redistribution layers provide electrical routing adapting die-level bump pitch (micro-bumps 10-40 μm spacing) to substrate-level ball pitch (solder balls 100-500 μm spacing). Direct routing impossible — would require impractical copper-line density at 10 μm pitch with 1 μm thickness. RDL solution: deposit multiple metal layers on planar substrate surface; each layer enables local routing and vias transition signals between layers. Typical RDL: 3-4 metal layers (copper), 3-5 μm pitch, separated by 2-5 μm dielectric. This enables arbitrary routing complexity — signals transition from dense 20 μm pitch bumps, redistribute through RDL, and route to substrate-level 100-200 μm pitch pads.

Metal Layers and Routing

• Copper Deposition: Electrochemical plating deposits ultra-pure copper from copper sulfate solutions; thickness 1-3 μm per layer typical
• Trace Geometry: Minimum trace width and spacing 1-5 μm; 3 μm typical for cost-effective production, 1 μm for advanced designs requiring maximum density
• High-Density Integration: Multiple signal layers enable complex routing; signal routing density approaches 500 mil/layer achievable through precise lithography
• Power Delivery: Dedicated power/ground layers carry supply current; wide traces (10-50 μm) reduce voltage drop across large chiplet arrays

Dielectric Materials and Layer Stack

• Polymer Dielectrics: Polyimide (PI) most common — 2-5 μm thickness, low cost, well-established processes; dielectric constant κ ~3.5
• Low-κ Alternatives: Benzocyclobutene (BCB, κ ~2.6), parylene (κ ~3), and porous polymers (κ ~2.2) reduce parasitic capacitance improving signal integrity for high-frequency applications
• Via Formation: Vias created through photolithography and etch (chemical or plasma) opening small holes; vias filled with copper plating
• Planarization: Chemical-mechanical polish (CMP) removes excess copper after plating, creating flat surface for subsequent dielectric/metal deposition

Fan-Out Wafer-Level Packaging (FOWLP) RDL

• Die Placement: Chiplets bonded directly to RDL surface (no interposer) through micro-bump bonding; dies positioned with gaps between enabling RDL routing underneath
• Reconstituted Wafer: After die bonding, underfill material creates mechanical stability; subsequent RDL processing treated as standard wafer enabling batch processing economics
• Chip-First vs Chip-Last: Chip-first (dies bonded before RDL) enables rework capability but complicates RDL lithography (features must align around existing dies); chip-last (RDL complete, then dies bonded) enables finer RDL pitch but limits rework flexibility

Signal Integrity and High-Speed RDL

• Impedance Control: Trace width, spacing, and dielectric thickness tuned for target impedance (typically 50-75 Ω differential); variations in these parameters cause impedance discontinuities generating reflections
• Loss Management: Copper surface roughness (1-2 μm) contributes to signal loss through increased scattering; smooth plating processes reduce roughness improving transmission
• Crosstalk Mitigation: Spacing between signal traces (3-5x trace width typical) limits capacitive coupling; guard traces grounded at regular intervals shield sensitive signals
• Via Stitching: Multiple small vias in parallel reduce via inductance critical for power-ground connections

Advanced RDL Concepts

• Buried Traces: Metal lines embedded within dielectric (not on surface) enable higher density through layering; manufacturing complexity increases significantly
• Sequential Build-Up: Temporary carrier substrates enable high-layer-count RDL stacks (10+ layers) through sequential deposition and bonding cycles
• Embedded Components: Capacitors, resistors, and inductors embedded in RDL layers reduce printed-circuit-board (PCB) BOM and improve power delivery

Integration with Advanced Packaging

• Chiplet Rooting: RDL routes signals between multiple chiplets enabling heterogeneous integration (high-performance CPU core, GPU core, memory, I/O on separate chiplets with independent optimization)
• Dies Assembly: Multiple dies stacked vertically through through-silicon-vias (TSVs) and RDL bridging multiple stack levels
• Substrate Transition: RDL connects to substrate pads enabling subsequent PCB assembly through solder-ball reflow

Manufacturing Challenges

• Defect Control: High layer count and minimum-pitch features increase defect probability; particle contamination, lithography misalignment, and etch anomalies common yield-limiting factors
• Planarity: CMP process uniformity critical — non-uniform polish creates height variation (±10 nm tolerance) complicating subsequent lithography
• Thermal Management: Thin dielectric layers (<2 μm) provide limited thermal isolation; copper traces conduct heat away from dies enabling cooling

Closing Summary

Redistribution layer technology represents the essential signal routing infrastructure enabling advanced heterogeneous packaging through flexible multilayer interconnection — transforming chiplet integration economics by providing dense routing bridges between high-density die bumps and substrate-level connections.