RDMA allows one host or accelerator to read, write, or exchange messages with registered remote memory while avoiding the conventional remote CPU kernel data path. It reduces copies, context switches, CPU overhead and latency for distributed AI, storage and HPC communication. InfiniBand provides native RDMA semantics, RoCEv2 carries RDMA over routable UDP/IP Ethernet, and iWARP uses TCP. Microsecond-class latency is possible in controlled systems, but end-to-end behavior depends on NIC, switch, congestion and software. A production definition states the service or pipeline boundary, tenants, workload and data classes, dependency graph, consistency and durability expectations, capacity envelope, latency and availability objectives, failure model, trust zones, deployment units, ownership, and evidence required for release. Architecture diagrams and service-level indicators must refer to the same boundary. An RDMA contract names transport, verbs, queue pair type, memory registration, permissions, completion semantics, ordering, MTU, congestion/loss policy, topology, GPU-direct path and failure recovery.

Architecture, control plane, and operating behavior. Applications post work requests to send and receive queues, an RNIC performs DMA against pinned and registered memory, packets cross the fabric, the remote RNIC accesses authorized memory, and completion queues notify software. One-sided reads/writes can avoid remote CPU execution. Protection domains and memory keys restrict access; queue pairs maintain transport state; completion polling avoids interrupts; zero-copy paths reduce staging. GPUDirect RDMA lets NICs access GPU memory through supported PCIe/topology paths, and NCCL-class collectives use RDMA for inter-node exchange. InfiniBand reliable connected and unreliable datagram modes, RoCEv2, iWARP, send/receive, RDMA read/write, atomics, GPU direct, user-space verbs and storage protocols offer different reliability and operational characteristics. The operational stack spans clients and producers, APIs or ingestion, queues and schedulers, stateless and stateful compute, accelerators, memory and storage, network fabrics, identity and policy, artifact registries, observability, automation, and human operations. Control-plane decisions and data-plane work are separated so overload or compromise in one does not silently corrupt the other. Evaluation combines correctness and model quality with throughput, p50/p95/p99 latency, queue depth, saturation, availability, error and retry rates, freshness, data loss, recovery time, recovery point, capacity, utilization, memory, network, energy, cost, and operator toil. Service-level objectives use user-visible good events, explicit windows, and error budgets rather than infrastructure uptime alone.

Implementation, infrastructure, and failure modes. Pin and register bounded buffers, reuse registrations, size queues, batch work requests, poll adaptively, map NICs to local GPUs, configure PFC/ECN or alternative congestion controls for RoCE, monitor retransmission and preserve fallback paths. RNIC DMA engines, PCIe root locality, IOMMU, GPU BAR/memory support, switch buffers, link rate, optics, MTU and CPU cache behavior determine results. Kernel bypass does not eliminate physical or fabric latency. Stale memory keys, use-after-free, queue exhaustion, lossless-Ethernet deadlock, congestion spreading, asymmetric routing, completion mishandling, memory-registration pressure and topology misplacement can cause corruption or stalls. Implementation favors immutable artifacts, declarative configuration, typed schemas, idempotent operations, bounded retries with jitter, deadlines, backpressure, health and readiness probes, least privilege, encrypted transport and storage, progressive rollout, reproducible environments, and complete telemetry. Automation has dry-run, approval, audit, and rollback paths. AI infrastructure joins CPUs, GPUs or NPUs, HBM, host memory, NICs and DPUs, PCIe and scale-up links, leaf-spine networks, local and shared storage, power delivery, and cooling. Topology, NUMA locality, bandwidth, failure domains, thermal headroom, and accelerator memory determine delivered behavior and must be visible to schedulers. Common failures include retry storms, queue collapse, stale health signals, split brain, partial writes, incompatible schemas, silent data corruption, time skew, dependency amplification, capacity fragmentation, noisy neighbors, credential leakage, unbounded state, monitoring blind spots, and recovery procedures that exist only on paper. A healthy component does not prove a healthy user journey.

Verification, security, and lifecycle controls. Test permissions and invalid keys, ordering, large/small messages, bidirectional load, congestion, packet loss, link flap, NIC reset, queue exhaustion, GPU-direct parity and application collectives under failure. Message latency, bandwidth, message rate, CPU use, queue depth, completion time, retransmission, ECN/PFC, congestion, registration cost, GPU stalls and collective tail matter. RDMA exposes powerful memory access; enforce least privilege, network segmentation, trusted drivers/firmware, IOMMU, key lifecycle, tenant isolation and audited configuration. Verification combines unit, contract and property tests, schema compatibility, load and soak tests, chaos and fault injection, security review, backup restoration, failover and rollback drills, dependency degradation, regional evacuation where applicable, data reconciliation, shadow traffic, canaries, and end-to-end synthetic checks. Tests run against production-like scale and permissions. Source, data, configuration, environment, model, registry metadata, infrastructure definition, dependency, image, driver, firmware, deployment, experiment, approval, incident, and rollback artifacts remain linked. Continuous controls detect drift, expired credentials, unowned resources, stale backups, regressions, policy exceptions, and unsupported versions. Owners define access, segregation of duties, data classification, residency, retention and deletion, vendor and supply-chain review, incident severity, communications, audit evidence, RTO/RPO or SLO exceptions, cost attribution, and change authority. Sensitive model and experiment artifacts receive the same integrity and confidentiality controls as source and production data.

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Selection and production application. Use InfiniBand for integrated HPC fabrics, RoCE when Ethernet economics and operations can support congestion engineering, and iWARP when TCP behavior matters; benchmark the actual topology. Distributed training collectives, GPU-to-GPU transfer, HPC, NVMe over Fabrics, distributed databases and low-latency storage use RDMA. RDMA performance spans application buffers, collective algorithms, GPU/NIC locality, PCIe, switches, congestion control, drivers, firmware and observability. The useful optimization and reliability boundary is the complete user-facing system. Improving a model server, network, registry, deployment controller, or pipeline stage can move the bottleneck or weaken consistency, safety, recoverability, and cost elsewhere, so decisions are validated end to end. A production definition states the service or pipeline boundary, tenants, workload and data classes, dependency graph, consistency and durability expectations, capacity envelope, latency and availability objectives, failure model, trust zones, deployment units, ownership, and evidence required for release. Architecture diagrams and service-level indicators must refer to the same boundary. Evaluation combines correctness and model quality with throughput, p50/p95/p99 latency, queue depth, saturation, availability, error and retry rates, freshness, data loss, recovery time, recovery point, capacity, utilization, memory, network, energy, cost, and operator toil. Service-level objectives use user-visible good events, explicit windows, and error budgets rather than infrastructure uptime alone. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.