real-time systems is computing systems whose correctness depends on both the produced result and the time at which it is delivered. Hard real-time behavior protects flight, braking, medical, industrial, and robotics functions, while soft real time shapes media and interactive AI quality.

Architecture and principles. Hard deadlines cannot be missed without system failure; firm deadlines make late results useless; soft deadlines tolerate occasional degradation. Tasks have release times, periods, worst-case execution, deadlines, priorities, and resource dependencies. Rate-monotonic and deadline-monotonic policies assign fixed priorities; earliest-deadline-first uses dynamic priority. Schedulability analysis proves utilization and interference assumptions rather than relying on average latency.

Execution and system behavior. Preemptive kernels switch to higher-priority ready tasks. Interrupt latency, context-switch time, critical sections, DMA, caches, buses, memory arbitration, and driver behavior contribute jitter. Priority inheritance or ceiling protocols bound priority inversion. Time-triggered designs schedule communication and compute statically. Watchdogs and independent safety mechanisms handle missed timing or faults. Tail latency and maximum blocking matter more than mean response.

Applications and semiconductor impact. FreeRTOS provides a compact commercial-friendly kernel; Zephyr combines RTOS services, drivers, connectivity, and security; VxWorks targets safety and industrial certification; QNX uses a microkernel and strong automotive presence. AI perception may need sub-10-ms-class inference in autonomous or robotic loops, but sensor exposure, preprocessing, queues, accelerator dispatch, postprocessing, network, and actuator response all consume the budget.

Trade-offs and current engineering. Worst-case execution on modern cached multicore SoCs is difficult because speculation, shared caches, DRAM, thermal throttling, and accelerators introduce variability. Isolation, core pinning, cache partitioning, memory QoS, bounded allocators, static configuration, and mixed-criticality scheduling help. Test measurements support but do not replace analytical bounds for safety-critical claims.

Verification and lifecycle. A production implementation begins with explicit terminal conditions, operating ranges, loading, accuracy, noise, latency, efficiency, area, cost, lifetime, and fault behavior. Schematic or architectural models establish feasibility; extracted, package, board, thermal, and control-loop models then reveal interactions hidden by ideal sources and loads. Verification spans process, voltage, temperature, mismatch, aging, startup, shutdown, overload, brownout, and recovery. Teams should define measurement bandwidth, observation point, stimulus, pass limit, guard band, and statistical confidence before simulation. Layout review covers current return, thermal gradients, matching, parasitic coupling, electromigration, voltage stress, latch-up, ESD paths, and test access. Correlation retains netlists, models, scripts, tool versions, raw results, lab conditions, calibration status, and explanations for outliers. This evidence turns a nominal design into a reproducible component that can be signed off across device, circuit, package, firmware, and system teams. Corner selection should follow sensitivity rather than blindly combining labels. Deterministic sweeps expose monotonic trends, targeted Monte Carlo analysis estimates distribution tails, and importance sampling can explore rare failures. Reviewers should distinguish model uncertainty from manufacturing variation and avoid claiming yield from too few samples. The interface contract must state what happens outside normal operation. Open and short terminals, reverse polarity, hot plug, disabled bias, floating control pins, clock loss, thermal shutdown, current limiting, and repeated fault cycling often determine field reliability even though they are absent from the nominal transfer function. Dynamic behavior deserves the same attention as steady state. Settling, overshoot, ringing, slew, recovery from saturation, mode transitions, and interaction with external poles can violate a system limit long before a DC endpoint does. Time-domain tests should include realistic edge rates and source impedance. Noise should be referred to the signal or supply point that matters to the application and integrated only over a stated bandwidth. Thermal, flicker, quantization, switching, reference, substrate, and electromagnetic contributions may combine differently across modes, so a single spot-noise number rarely completes the specification. Power and thermal claims should include quiescent, active, transient, and fault states. Average efficiency can hide localized current density or hot spots; electrothermal simulation and temperature-aware device models connect electrical stress to lifetime, drift, and protection thresholds. Physical design must preserve the assumptions behind the schematic. Symmetry, common-centroid placement, dummies, shielding, guard rings, Kelvin sensing, wide current paths, via arrays, controlled coupling, and quiet reference routing are selected according to the dominant error rather than applied as decoration. Production test strategy is part of design. Trim range, observability, loopback modes, built-in self-test, boundary conditions, test time, and instrument uncertainty determine which specifications can be guaranteed economically. Characterization across wafers and lots should feed model and guard-band updates. System telemetry can extend laboratory correlation into deployed products. Error counters, calibration codes, temperatures, supply monitors, fault flags, margin measurements, and performance events help distinguish random failures from systematic drift without exposing sensitive implementation details. A useful comparison normalizes alternatives at equal output requirement and environment. Peak headline values can be misleading when bandwidth, drive, voltage, area, cooling, external components, calibration, or reliability differs; the decision record should name the workload and weighting used. Cross-functional review should trace each requirement from physical mechanism through circuit behavior to application impact. That trace prevents duplicated margin, exposes assumptions that span ownership boundaries, and makes later process or package substitutions safer. Corner selection should follow sensitivity rather than blindly combining labels. Deterministic sweeps expose monotonic trends, targeted Monte Carlo analysis estimates distribution tails, and importance sampling can explore rare failures. Reviewers should distinguish model uncertainty from manufacturing variation and avoid claiming yield from too few samples. The interface contract must state what happens outside normal operation. Open and short terminals, reverse polarity, hot plug, disabled bias, floating control pins, clock loss, thermal shutdown, current limiting, and repeated fault cycling often determine field reliability even though they are absent from the nominal transfer function. Dynamic behavior deserves the same attention as steady state. Settling, overshoot, ringing, slew, recovery from saturation, mode transitions, and interaction with external poles can violate a system limit long before a DC endpoint does. Time-domain tests should include realistic edge rates and source impedance. Noise should be referred to the signal or supply point that matters to the application and integrated only over a stated bandwidth. Thermal, flicker, quantization, switching, reference, substrate, and electromagnetic contributions may combine differently across modes, so a single spot-noise number rarely completes the specification.

<svg viewBox="0 0 960 380" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,sans-serif">
<rect width="960" height="380" rx="12" fill="#1a1a17"/>
<defs><marker id="arrow" markerWidth="8" markerHeight="8" refX="7" refY="4" orient="auto"><path d="M0,0 L8,4 L0,8 Z" fill="#6fafaf"/></marker></defs>
<text x="480" y="30" text-anchor="middle" font-size="16" font-weight="700" fill="#f4f1e8">Priority-preemptive real-time schedule</text>
<line x1="80" y1="310" x2="910" y2="310" stroke="#c9c3f2"/><g font-size="10" fill="#f4f1e8"><text x="30" y="105">High</text><text x="30" y="185">Medium</text><text x="30" y="265">Low</text></g><g><rect x="110" y="75" width="150" height="45" fill="#bf4040"/><rect x="520" y="75" width="130" height="45" fill="#bf4040"/><rect x="300" y="155" width="180" height="45" fill="#e0913a"/><rect x="650" y="155" width="150" height="45" fill="#e0913a"/><rect x="80" y="235" width="30" height="45" fill="#6fbf6f"/><rect x="260" y="235" width="40" height="45" fill="#6fbf6f"/><rect x="480" y="235" width="40" height="45" fill="#6fbf6f"/><rect x="800" y="235" width="90" height="45" fill="#6fbf6f"/></g><text x="185" y="65" text-anchor="middle" font-size="10" fill="#c9c3f2">High-priority arrivals preempt lower work</text><text x="480" y="350" text-anchor="middle" font-size="10" fill="#8fe3bd">Deadline proof uses worst-case execution, blocking, interference, and release jitter</text>
</svg>

Connection to CFS platform. Use CFS architecture, accelerator, memory, cloud, edge, security, networking, power, and system simulators with linked glossary topics to connect foundational concepts to measurable semiconductor and deployment choices.