<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 760 470" font-family="Segoe UI,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">RDL: copper-on-polymer routing that re-pitches die I/O to the board</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Thin-film copper in spin-coated polymer re-routes fine die pads to coarse ball pitch — fanning I/O past the die edge</text><!-- ===== PANEL 1 ===== --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="36" y="92" fill="#38bdf8" font-size="14" font-weight="700">1 · Pitch translation</text><!-- die + fine pads --><rect x="66" y="108" width="120" height="24" rx="3" fill="#1c2733" stroke="#6f8fb0"/><text x="126" y="124" text-anchor="middle" fill="#adb5bd" font-size="9.5">die — fine pads</text><g fill="#b8732e"><circle cx="72" cy="137" r="2"/><circle cx="82" cy="137" r="2"/><circle cx="92" cy="137" r="2"/><circle cx="102" cy="137" r="2"/><circle cx="112" cy="137" r="2"/><circle cx="122" cy="137" r="2"/><circle cx="132" cy="137" r="2"/><circle cx="142" cy="137" r="2"/><circle cx="152" cy="137" r="2"/><circle cx="162" cy="137" r="2"/><circle cx="172" cy="137" r="2"/><circle cx="182" cy="137" r="2"/></g><!-- RDL region with fan traces --><rect x="38" y="144" width="186" height="36" rx="2" fill="#14202b" stroke="#30363d"/><text x="131" y="165" text-anchor="middle" fill="#586b7a" font-size="8.5">RDL</text><g stroke="#b8732e" stroke-width="1.3" fill="none"><line x1="77" y1="144" x2="52" y2="180"/><line x1="97" y1="144" x2="82" y2="180"/><line x1="117" y1="144" x2="110" y2="180"/><line x1="137" y1="144" x2="140" y2="180"/><line x1="160" y1="144" x2="170" y2="180"/><line x1="180" y1="144" x2="200" y2="180"/></g><!-- coarse balls --><g fill="#e0b13a"><circle cx="52" cy="185" r="4"/><circle cx="82" cy="185" r="4"/><circle cx="110" cy="185" r="4"/><circle cx="140" cy="185" r="4"/><circle cx="170" cy="185" r="4"/><circle cx="200" cy="185" r="4"/></g><text x="126" y="202" text-anchor="middle" fill="#8b949e" font-size="8.5">coarse ball pitch</text><text x="36" y="224" fill="#adb5bd" font-size="11">RDL turns tight die-pad pitch into</text><text x="36" y="239" fill="#adb5bd" font-size="11">board-friendly ball pitch —</text><text x="36" y="264" fill="#38bdf8" font-size="11" font-weight="700">and fans I/O past the die edge.</text><text x="36" y="289" fill="#8b949e" font-size="10.5">~10–40 µm pads in →</text><text x="36" y="304" fill="#8b949e" font-size="10.5">~100–500 µm balls out.</text><text x="36" y="329" fill="#8b949e" font-size="10.5">The enabling interconnect for</text><text x="36" y="343" fill="#8b949e" font-size="10.5">WLCSP, fan-out and chiplets.</text><!-- ===== PANEL 2 ===== --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="283" y="92" fill="#38bdf8" font-size="14" font-weight="700">2 · The copper/polymer stack</text><text x="330" y="110" fill="#adb5bd" font-size="8">die pad</text><rect x="312" y="112" width="14" height="8" fill="#b8732e"/><!-- polymer block --><rect x="300" y="118" width="140" height="80" rx="2" fill="#241a12" stroke="#5a4632"/><!-- M1 --><rect x="308" y="132" width="66" height="6" fill="#b8732e"/><text x="310" y="130" fill="#f0d9b5" font-size="8">M1</text><rect x="368" y="132" width="6" height="20" fill="#d08a4a"/><!-- M2 --><rect x="360" y="150" width="66" height="6" fill="#b8732e"/><text x="362" y="148" fill="#f0d9b5" font-size="8">M2</text><rect x="418" y="150" width="6" height="22" fill="#d08a4a"/><!-- M3 --><rect x="336" y="170" width="88" height="6" fill="#b8732e"/><text x="338" y="168" fill="#f0d9b5" font-size="8">M3</text><rect x="360" y="176" width="6" height="18" fill="#d08a4a"/><text x="384" y="146" fill="#9fd8ef" font-size="8">via</text><!-- UBM + ball --><rect x="354" y="192" width="18" height="5" fill="#586069"/><circle cx="363" cy="203" r="6" fill="#e0b13a"/><text x="376" y="206" fill="#adb5bd" font-size="8">UBM + ball</text><text x="283" y="226" fill="#c9d1d9" font-size="10.5">3–4 copper layers in polymer;</text><text x="283" y="241" fill="#c9d1d9" font-size="10.5">vias step signals between them.</text><text x="283" y="264" fill="#c4b5fd" font-size="10.5">PI: Dk ~3.5   ·   PBO: Dk ~2.6</text><text x="283" y="285" fill="#adb5bd" font-size="10.5">Line/space scales from</text><text x="283" y="300" fill="#adb5bd" font-size="10.5">10/10 µm down to 2/2 µm.</text><text x="283" y="325" fill="#8b949e" font-size="10.5">Finer L/S → more routing per</text><text x="283" y="339" fill="#8b949e" font-size="10.5">layer, but harder to yield.</text><!-- ===== PANEL 3 ===== --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="530" y="92" fill="#38bdf8" font-size="14" font-weight="700">3 · Building it &amp; the knobs</text><g font-size="9.5" font-weight="700" fill="#0d1117"><circle cx="537" cy="112" r="6.5" fill="#38bdf8"/><text x="537" y="115" text-anchor="middle">1</text><circle cx="537" cy="132" r="6.5" fill="#38bdf8"/><text x="537" y="135" text-anchor="middle">2</text><circle cx="537" cy="152" r="6.5" fill="#38bdf8"/><text x="537" y="155" text-anchor="middle">3</text><circle cx="537" cy="172" r="6.5" fill="#38bdf8"/><text x="537" y="175" text-anchor="middle">4</text><circle cx="537" cy="192" r="6.5" fill="#38bdf8"/><text x="537" y="195" text-anchor="middle">5</text></g><text x="549" y="115" fill="#c9d1d9" font-size="10">Spin-coat polymer, bake, cure</text><text x="549" y="135" fill="#c9d1d9" font-size="10">Open vias — laser or litho</text><text x="549" y="155" fill="#c9d1d9" font-size="10">Sputter a copper seed layer</text><text x="549" y="175" fill="#c9d1d9" font-size="10">Electroplate Cu, pattern, etch</text><text x="549" y="195" fill="#c9d1d9" font-size="10">Repeat per layer (2–8 layers)</text><line x1="530" y1="208" x2="724" y2="208" stroke="#30363d"/><text x="530" y="228" fill="#e0b13a" font-size="11.5" font-weight="700">The hard parts</text><g fill="#e0b13a"><circle cx="534" cy="241" r="2.6"/><circle cx="534" cy="256" r="2.6"/><circle cx="534" cy="271" r="2.6"/><circle cx="534" cy="286" r="2.6"/></g><text x="544" y="244" fill="#adb5bd" font-size="10.5">layer-to-layer overlay/alignment</text><text x="544" y="259" fill="#adb5bd" font-size="10.5">fine L/S yield (down to 2/2 µm)</text><text x="544" y="274" fill="#adb5bd" font-size="10.5">copper plating uniformity</text><text x="544" y="289" fill="#adb5bd" font-size="10.5">polymer-cure stress → warpage</text><text x="530" y="315" fill="#f87171" font-size="10.5" font-weight="700">Overlay and plating set how tight</text><text x="530" y="329" fill="#f87171" font-size="10.5" font-weight="700">the RDL can be pushed.</text><!-- ===== BOTTOM CARDS ===== --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="36" y="406" fill="#38bdf8" font-size="12.5" font-weight="700">Pitch translator</text><text x="36" y="424" fill="#adb5bd" font-size="10">Converts µm-pitch die bumps into</text><text x="36" y="437" fill="#adb5bd" font-size="10">board-friendly ball pitch and fans</text><text x="36" y="450" fill="#adb5bd" font-size="10">I/O past the die edge.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="283" y="406" fill="#c4b5fd" font-size="12.5" font-weight="700">Copper on polymer</text><text x="283" y="424" fill="#adb5bd" font-size="10">Plated copper traces sit in spin-</text><text x="283" y="437" fill="#adb5bd" font-size="10">coated PI/PBO; stack 2–8 layers</text><text x="283" y="450" fill="#adb5bd" font-size="10">with vias between them.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="530" y="406" fill="#e0b13a" font-size="12.5" font-weight="700">Alignment &amp; plating gate yield</text><text x="530" y="424" fill="#adb5bd" font-size="10">Layer overlay, fine line/space and</text><text x="530" y="437" fill="#adb5bd" font-size="10">copper plating uniformity set how</text><text x="530" y="450" fill="#adb5bd" font-size="10">tight RDL can go.</text></svg>

Redistribution Layer (RDL) is a thin-film metal wiring layer fabricated on the surface of a die or wafer that reroutes electrical connections from their original pad locations to new positions — enabling fan-out of tightly spaced chip I/O pads to a wider-pitch bump array compatible with the substrate or next-level interconnect, and providing the backside wiring that connects revealed TSV tips to micro-bumps or hybrid bonding pads in 3D integration.

What Is a Redistribution Layer?

• Definition: One or more layers of patterned metal traces (copper) and dielectric insulation (polyimide, PBO, or inorganic) fabricated on a wafer or die surface using thin-film lithography and plating processes, creating a routing network that translates between the chip's native pad layout and the package's required bump pattern.
• Fan-Out: RDL extends connections from the die edge outward beyond the die footprint — fan-out wafer-level packaging (FOWLP) uses RDL to redistribute I/O from a small die to a larger package area, increasing the number of connections without increasing die size.
• Fan-In: RDL routes connections from peripheral pads to an area array under the die — converting a wire-bond pad layout to a flip-chip bump array without redesigning the chip.
• Backside RDL: In 3D integration, RDL on the thinned wafer backside connects revealed TSV tips to micro-bumps or bonding pads — this backside RDL is the critical wiring layer that enables electrical connection between stacked dies.

Why RDL Matters

• I/O Density: Modern SoCs require 5,000-50,000+ I/O connections — RDL enables routing this many connections from the chip's pad pitch (40-100 μm) to the package's bump pitch (100-400 μm) or to fine-pitch hybrid bonding pads (< 10 μm).
• FOWLP: Fan-out wafer-level packaging (TSMC InFO, ASE/Daishin) uses RDL as the primary interconnect — Apple's A-series and M-series processors use InFO-WLP with multi-layer RDL for high-density packaging.
• 3D Backside Connection: After TSV reveal, the backside RDL provides the routing from TSV tips to the bonding interface — without RDL, each TSV would need to align directly with a pad on the next die, which is impractical.
• Cost Reduction: RDL-based packaging (FOWLP, fan-in WLP) eliminates the need for expensive ceramic or organic substrates in many applications, reducing package cost by 20-50%.

RDL Process and Materials

• Dielectric: Polyimide (PI), polybenzoxazole (PBO), or inorganic SiO₂/Si₃N₄ — provides insulation between RDL metal layers and passivation of the die surface. Polymer dielectrics are preferred for their low stress and thick-film capability.
• Metal: Copper deposited by sputtering (seed) + electroplating (bulk) — patterned by photolithography and etching or by semi-additive plating (SAP) where copper is plated only in photoresist openings.
• Line/Space: Production RDL achieves 2/2 μm line/space for advanced FOWLP — pushing toward 1/1 μm for next-generation high-density fan-out.
• Layer Count: 1-4 RDL layers for standard FOWLP, up to 6-8 layers for high-density applications — each layer adds routing capacity but increases cost and process complexity.

Redistribution layers are the essential routing technology that bridges the gap between chip-level and package-level interconnect pitches — providing the thin-film wiring that fans out dense chip I/O to package bumps, connects TSV tips to bonding interfaces, and enables the wafer-level packaging architectures that deliver the I/O density and cost efficiency demanded by modern semiconductor products.