RDL (Redistribution Layer) Process is patterned metal routing on polymer dielectric enabling fine-pitch signal routing in advanced packaging and chiplet integration.

Polymer Dielectric Materials:

• Polyimide (PI): industry standard, low Dk (~3.5), established process windows
• Polybenzoxazole (PBO): lower Dk (~2.6), better thermal stability, emerging adoption
• Dielectric thickness: 5-15 µm typical (thicker = lower capacitance)
• Processing: spin-coat → soft bake → hard cure (thermal or UV depending on chemistry)
• Adhesion: surface priming required (plasma, silane coupling agent)

RDL Trace Design:

• Trace width/spacing: L/S scaling from 10/10 µm down to 2/2 µm possible
• Advanced: sub-1 µm L/S in research labs (cost-prohibitive for production)
• Via density: drives routing efficiency (finer via = more routing layers needed)
• Impedance control: adjust line thickness for 50Ω characteristic impedance (RF applications)

Multi-Layer RDL Architecture:

• Layer count: 2-8 layers typical for complex redistribution
• Via stacking: multiple vias through different layers for vertical connectivity
• Layer-to-layer alignment: critical tolerance (<1 µm for fine-pitch)
• Routing optimization: automated tools (Cadence, Synopsys) for efficient placement

Copper Seed and Electroplating:

• Seed layer: sputtered Ti/Cu (100-200 nm TaN/Ta liner + Cu)
• Seed adhesion: critical for fine-pitch trace adhesion
• Electroplating: ECD Cu plating (superfilling enabled by accelerators/suppressors)
• Plating thickness: 1-5 µm typical (current-carrying capacity dependent)

Via Formation Methods:

• Laser drilling: excimer laser (248 nm, 308 nm) for via opening in dielectric
• Photolithography: alternative for finest vias (<5 µm feasible)
• Via aspect ratio: ~1:1 preferred (equal width/depth)
• Via filling: electroplated copper, potential for trapped voids

RDL Mechanical Reliability:

• Coefficient of thermal expansion (CTE): dielectric/metal CTE mismatch stress
• Dielectric CTE: polyimide ~10-20 ppm/K (vs Cu ~17 ppm/K)
• PBO CTE slightly better matched to Cu
• Solder reflow thermal cycling: mechanical failure modes (delamination, cracking)

Application Examples:

• Chiplet interposer: RDL fans out chiplet bumps to substrate pads
• 3D stacking: RDL on top of die for vertical interconnect
• Advanced packages (FOWLP/CoWoS): RDL primary routing layer
• RF applications: impedance-controlled traces

Process Integration Challenges:

• Dielectric adhesion: requires surface treatment (plasma, priming)
• Via fill uniformity: small vias prone to pinhole voids
• Copper plating grain growth: affects electromigration reliability
• CMP uniformity: must planarize copper across large area

RDL technology critical enabler for chiplet ecosystem—fine-pitch capability and proven reliability support next-decade heterogeneous integration architectures.