<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 760 470" font-family="Segoe UI,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">RDL: copper-on-polymer routing that re-pitches die I/O to the board</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Thin-film copper in spin-coated polymer re-routes fine die pads to coarse ball pitch — fanning I/O past the die edge</text><!-- ===== PANEL 1 ===== --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="36" y="92" fill="#38bdf8" font-size="14" font-weight="700">1 · Pitch translation</text><!-- die + fine pads --><rect x="66" y="108" width="120" height="24" rx="3" fill="#1c2733" stroke="#6f8fb0"/><text x="126" y="124" text-anchor="middle" fill="#adb5bd" font-size="9.5">die — fine pads</text><g fill="#b8732e"><circle cx="72" cy="137" r="2"/><circle cx="82" cy="137" r="2"/><circle cx="92" cy="137" r="2"/><circle cx="102" cy="137" r="2"/><circle cx="112" cy="137" r="2"/><circle cx="122" cy="137" r="2"/><circle cx="132" cy="137" r="2"/><circle cx="142" cy="137" r="2"/><circle cx="152" cy="137" r="2"/><circle cx="162" cy="137" r="2"/><circle cx="172" cy="137" r="2"/><circle cx="182" cy="137" r="2"/></g><!-- RDL region with fan traces --><rect x="38" y="144" width="186" height="36" rx="2" fill="#14202b" stroke="#30363d"/><text x="131" y="165" text-anchor="middle" fill="#586b7a" font-size="8.5">RDL</text><g stroke="#b8732e" stroke-width="1.3" fill="none"><line x1="77" y1="144" x2="52" y2="180"/><line x1="97" y1="144" x2="82" y2="180"/><line x1="117" y1="144" x2="110" y2="180"/><line x1="137" y1="144" x2="140" y2="180"/><line x1="160" y1="144" x2="170" y2="180"/><line x1="180" y1="144" x2="200" y2="180"/></g><!-- coarse balls --><g fill="#e0b13a"><circle cx="52" cy="185" r="4"/><circle cx="82" cy="185" r="4"/><circle cx="110" cy="185" r="4"/><circle cx="140" cy="185" r="4"/><circle cx="170" cy="185" r="4"/><circle cx="200" cy="185" r="4"/></g><text x="126" y="202" text-anchor="middle" fill="#8b949e" font-size="8.5">coarse ball pitch</text><text x="36" y="224" fill="#adb5bd" font-size="11">RDL turns tight die-pad pitch into</text><text x="36" y="239" fill="#adb5bd" font-size="11">board-friendly ball pitch —</text><text x="36" y="264" fill="#38bdf8" font-size="11" font-weight="700">and fans I/O past the die edge.</text><text x="36" y="289" fill="#8b949e" font-size="10.5">~10–40 µm pads in →</text><text x="36" y="304" fill="#8b949e" font-size="10.5">~100–500 µm balls out.</text><text x="36" y="329" fill="#8b949e" font-size="10.5">The enabling interconnect for</text><text x="36" y="343" fill="#8b949e" font-size="10.5">WLCSP, fan-out and chiplets.</text><!-- ===== PANEL 2 ===== --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="283" y="92" fill="#38bdf8" font-size="14" font-weight="700">2 · The copper/polymer stack</text><text x="330" y="110" fill="#adb5bd" font-size="8">die pad</text><rect x="312" y="112" width="14" height="8" fill="#b8732e"/><!-- polymer block --><rect x="300" y="118" width="140" height="80" rx="2" fill="#241a12" stroke="#5a4632"/><!-- M1 --><rect x="308" y="132" width="66" height="6" fill="#b8732e"/><text x="310" y="130" fill="#f0d9b5" font-size="8">M1</text><rect x="368" y="132" width="6" height="20" fill="#d08a4a"/><!-- M2 --><rect x="360" y="150" width="66" height="6" fill="#b8732e"/><text x="362" y="148" fill="#f0d9b5" font-size="8">M2</text><rect x="418" y="150" width="6" height="22" fill="#d08a4a"/><!-- M3 --><rect x="336" y="170" width="88" height="6" fill="#b8732e"/><text x="338" y="168" fill="#f0d9b5" font-size="8">M3</text><rect x="360" y="176" width="6" height="18" fill="#d08a4a"/><text x="384" y="146" fill="#9fd8ef" font-size="8">via</text><!-- UBM + ball --><rect x="354" y="192" width="18" height="5" fill="#586069"/><circle cx="363" cy="203" r="6" fill="#e0b13a"/><text x="376" y="206" fill="#adb5bd" font-size="8">UBM + ball</text><text x="283" y="226" fill="#c9d1d9" font-size="10.5">3–4 copper layers in polymer;</text><text x="283" y="241" fill="#c9d1d9" font-size="10.5">vias step signals between them.</text><text x="283" y="264" fill="#c4b5fd" font-size="10.5">PI: Dk ~3.5   ·   PBO: Dk ~2.6</text><text x="283" y="285" fill="#adb5bd" font-size="10.5">Line/space scales from</text><text x="283" y="300" fill="#adb5bd" font-size="10.5">10/10 µm down to 2/2 µm.</text><text x="283" y="325" fill="#8b949e" font-size="10.5">Finer L/S → more routing per</text><text x="283" y="339" fill="#8b949e" font-size="10.5">layer, but harder to yield.</text><!-- ===== PANEL 3 ===== --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="530" y="92" fill="#38bdf8" font-size="14" font-weight="700">3 · Building it &amp; the knobs</text><g font-size="9.5" font-weight="700" fill="#0d1117"><circle cx="537" cy="112" r="6.5" fill="#38bdf8"/><text x="537" y="115" text-anchor="middle">1</text><circle cx="537" cy="132" r="6.5" fill="#38bdf8"/><text x="537" y="135" text-anchor="middle">2</text><circle cx="537" cy="152" r="6.5" fill="#38bdf8"/><text x="537" y="155" text-anchor="middle">3</text><circle cx="537" cy="172" r="6.5" fill="#38bdf8"/><text x="537" y="175" text-anchor="middle">4</text><circle cx="537" cy="192" r="6.5" fill="#38bdf8"/><text x="537" y="195" text-anchor="middle">5</text></g><text x="549" y="115" fill="#c9d1d9" font-size="10">Spin-coat polymer, bake, cure</text><text x="549" y="135" fill="#c9d1d9" font-size="10">Open vias — laser or litho</text><text x="549" y="155" fill="#c9d1d9" font-size="10">Sputter a copper seed layer</text><text x="549" y="175" fill="#c9d1d9" font-size="10">Electroplate Cu, pattern, etch</text><text x="549" y="195" fill="#c9d1d9" font-size="10">Repeat per layer (2–8 layers)</text><line x1="530" y1="208" x2="724" y2="208" stroke="#30363d"/><text x="530" y="228" fill="#e0b13a" font-size="11.5" font-weight="700">The hard parts</text><g fill="#e0b13a"><circle cx="534" cy="241" r="2.6"/><circle cx="534" cy="256" r="2.6"/><circle cx="534" cy="271" r="2.6"/><circle cx="534" cy="286" r="2.6"/></g><text x="544" y="244" fill="#adb5bd" font-size="10.5">layer-to-layer overlay/alignment</text><text x="544" y="259" fill="#adb5bd" font-size="10.5">fine L/S yield (down to 2/2 µm)</text><text x="544" y="274" fill="#adb5bd" font-size="10.5">copper plating uniformity</text><text x="544" y="289" fill="#adb5bd" font-size="10.5">polymer-cure stress → warpage</text><text x="530" y="315" fill="#f87171" font-size="10.5" font-weight="700">Overlay and plating set how tight</text><text x="530" y="329" fill="#f87171" font-size="10.5" font-weight="700">the RDL can be pushed.</text><!-- ===== BOTTOM CARDS ===== --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="36" y="406" fill="#38bdf8" font-size="12.5" font-weight="700">Pitch translator</text><text x="36" y="424" fill="#adb5bd" font-size="10">Converts µm-pitch die bumps into</text><text x="36" y="437" fill="#adb5bd" font-size="10">board-friendly ball pitch and fans</text><text x="36" y="450" fill="#adb5bd" font-size="10">I/O past the die edge.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="283" y="406" fill="#c4b5fd" font-size="12.5" font-weight="700">Copper on polymer</text><text x="283" y="424" fill="#adb5bd" font-size="10">Plated copper traces sit in spin-</text><text x="283" y="437" fill="#adb5bd" font-size="10">coated PI/PBO; stack 2–8 layers</text><text x="283" y="450" fill="#adb5bd" font-size="10">with vias between them.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="530" y="406" fill="#e0b13a" font-size="12.5" font-weight="700">Alignment &amp; plating gate yield</text><text x="530" y="424" fill="#adb5bd" font-size="10">Layer overlay, fine line/space and</text><text x="530" y="437" fill="#adb5bd" font-size="10">copper plating uniformity set how</text><text x="530" y="450" fill="#adb5bd" font-size="10">tight RDL can go.</text></svg>

Redistribution Layer (RDL) is the thin-film metal interconnect structure fabricated on wafer or package substrates that reroutes I/O connections from fine-pitch die pads (40-100μm) to coarser-pitch package balls (400-800μm) — enabling fan-out packaging, area array I/O, and heterogeneous integration with 2-10μm line/space lithography, 2-5 metal layers, and resistance <50 mΩ per connection.

RDL Structure:

• Metal Layers: Cu traces 2-10μm thick, 2-20μm wide; 2-5 metal levels depending on routing complexity; M1 connects to die pads, top metal connects to solder balls or bumps; via diameter 5-20μm connects metal layers
• Dielectric Layers: polymer (polyimide, BCB, PBO) or inorganic (SiO₂, SiN) dielectric 2-15μm thick between metal layers; provides electrical isolation, mechanical support, and stress buffer; dielectric constant 2.5-4.0 for polymers, 3.9-7.0 for inorganics
• Under-Bump Metallization (UBM): Ti/Cu or Ni/Au (5/500nm or 5μm electroless Ni / 0.05μm immersion Au) on top metal; provides solder-wettable surface and diffusion barrier; patterned by photolithography or through-mask plating
• Passivation: final polyimide or solder resist layer (5-20μm) protects RDL; openings for UBM and solder balls; provides environmental protection and electrical isolation

Fabrication Process (Wafer-Level):

• Passivation Opening: plasma etch or laser ablation opens die passivation to expose Al pads; opening diameter 30-80μm; Tokyo Electron Tactras or 3D-Micromac microSTRUCT laser
• Seed Layer Deposition: PVD Ti/Cu (50/500nm) sputtered on wafer; Ti provides adhesion to polyimide and Al pads; Cu provides seed for electroplating; Applied Materials Endura or Singulus TIMARIS
• Photoresist Patterning: thick photoresist (5-20μm) spin-coated and patterned; defines RDL traces and vias; Tokyo Electron CLEAN TRACK or SUSS MicroTec ACS200; 2-10μm line/space capability
• Cu Electroplating: Cu plated in photoresist openings; acid Cu sulfate bath; current density 10-30 mA/cm²; plating time 20-60 minutes for 2-10μm thickness; Lam Research SABRE or Applied Materials Raider

Dielectric Materials:

• Polyimide (PI): HD MicroSystems PI-2600 series; spin-coated 2-15μm per layer; soft bake 90-150°C, cure 300-350°C in N₂; dielectric constant 3.2-3.5; CTE 30-50 ppm/K; excellent planarization over topography
• Polybenzoxazole (PBO): HD MicroSystems Durimide; lower moisture absorption than PI (<0.5% vs 2-3%); cure temperature 300-400°C; dielectric constant 2.8-3.0; better dimensional stability; higher cost than PI
• Benzocyclobutene (BCB): Dow Cyclotene; low dielectric constant (2.65); cure temperature 200-250°C; excellent electrical properties for RF applications; poor adhesion requires adhesion promoter (AP3000)
• Inorganic Dielectrics: PECVD SiO₂ or SiN; deposited 0.5-2μm per layer; temperature 200-400°C; dielectric constant 3.9 (SiO₂) or 7.0 (SiN); better moisture barrier than polymers but higher stress and cost

Fan-Out RDL:

• eWLB (embedded Wafer-Level Ball Grid Array): dies placed face-down on temporary carrier; molded with epoxy mold compound (EMC); carrier removed; RDL fabricated on reconstituted wafer; enables fan-out I/O beyond die footprint
• InFO (Integrated Fan-Out): TSMC technology; multiple dies and passives embedded in mold compound; RDL connects dies and routes to package balls; used in Apple A-series processors; 2μm line/space, 4-5 metal layers
• FOWLP (Fan-Out Wafer-Level Package): generic term for fan-out technologies; RDL pitch 2-10μm enables high I/O count (>1000 balls); package thickness 200-600μm thinner than flip-chip BGA
• Advantages: low cost (wafer-level processing), thin profile, excellent electrical performance (short interconnects), scalable to large die sizes; challenges: warpage control, die shift during molding, RDL yield

Panel-Level RDL:

• Large Substrates: RDL fabricated on 510×515mm or 600×600mm glass or organic panels; 4-9× area vs 300mm wafers; economies of scale reduce cost per unit
• Equipment: modified PCB equipment for large panels; Shibaura Mechatronics panel plating, Nikon or Canon panel lithography, Toray or Ajinomoto dielectric coating
• Challenges: panel bow and warpage (>500μm across 600mm); non-uniform plating and lithography; handling and transport of large panels; yield learning ongoing
• Status: pilot production by ASE, Deca Technologies, and Nepes; cost benefits projected 20-40% vs wafer-level for large die and high-volume applications

Electrical Performance:

• Resistance: Cu trace resistance 17 mΩ/sq for 1μm thickness; typical RDL trace 2-5mm length, 5-10μm width, 3-5μm thickness → 10-50 mΩ resistance; via resistance 1-5 mΩ depending on diameter and aspect ratio
• Capacitance: trace-to-trace capacitance 0.1-0.5 pF/mm for 10μm spacing in polyimide (ε=3.3); trace-to-ground capacitance 0.5-2 pF/mm² for 5μm dielectric thickness
• Inductance: RDL trace inductance 0.5-2 nH/mm depending on width and ground plane proximity; lower than wire bonds (1-5 nH per bond) enabling higher frequency operation
• Signal Integrity: 2-5μm line/space RDL supports >10 GHz signaling; impedance control ±10% achieved through width and spacing design; ground planes in multi-layer RDL reduce crosstalk

Reliability:

• Thermal Cycling: JEDEC JESD22-A104 (-40°C to 125°C, 1000 cycles); failure mechanism: Cu trace cracking or delamination at dielectric interface; CTE mismatch between Cu (16.5 ppm/K), polyimide (30-50 ppm/K), and Si (2.6 ppm/K)
• Moisture Resistance: JEDEC JESD22-A120 (85°C/85% RH, 1000 hours); polyimide absorbs 2-3% moisture causing swelling and delamination; PBO and BCB have better moisture resistance (<0.5% absorption)
• Electromigration: Cu trace electromigration at high current density (>10⁵ A/cm²); mean time to failure (MTTF) = A·j⁻²·exp(Ea/kT) where Ea≈0.9 eV for Cu; design rule: current density <5×10⁴ A/cm² for 10-year lifetime
• Stress-Induced Voiding: voids form in Cu traces due to thermal stress; accelerated by moisture and high temperature; proper annealing (200-400°C, 30-60 min) after plating reduces voiding

Inspection and Metrology:

• Optical Inspection: automated optical inspection (AOI) checks line width, spacing, and defects; KLA 8 series or Camtek Falcon; resolution 0.5-1μm; detects opens, shorts, and dimensional defects
• Electrical Test: 4-wire Kelvin measurement of trace resistance; typical specification 10-50 mΩ; >100 mΩ indicates high resistance or open circuit; daisy-chain test structures enable continuity testing
• Cross-Section Analysis: FIB-SEM cross-sections verify layer thickness, via fill quality, and interface adhesion; Thermo Fisher Helios or Zeiss Crossbeam; destructive test on sample units
• Warpage Measurement: shadow moiré or laser profilometry measures package warpage; specification typically <100μm across package; excessive warpage causes assembly issues and reliability failures

Redistribution layers are the flexible interconnect fabric that enables modern advanced packaging — providing the routing density and electrical performance to connect fine-pitch die I/O to package-level interconnects while enabling fan-out architectures, heterogeneous integration, and system-in-package solutions that define the post-Moore's Law era of semiconductor scaling.