<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 760 470" font-family="Segoe UI,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">RDL: copper-on-polymer routing that re-pitches die I/O to the board</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Thin-film copper in spin-coated polymer re-routes fine die pads to coarse ball pitch — fanning I/O past the die edge</text><!-- ===== PANEL 1 ===== --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="36" y="92" fill="#38bdf8" font-size="14" font-weight="700">1 · Pitch translation</text><!-- die + fine pads --><rect x="66" y="108" width="120" height="24" rx="3" fill="#1c2733" stroke="#6f8fb0"/><text x="126" y="124" text-anchor="middle" fill="#adb5bd" font-size="9.5">die — fine pads</text><g fill="#b8732e"><circle cx="72" cy="137" r="2"/><circle cx="82" cy="137" r="2"/><circle cx="92" cy="137" r="2"/><circle cx="102" cy="137" r="2"/><circle cx="112" cy="137" r="2"/><circle cx="122" cy="137" r="2"/><circle cx="132" cy="137" r="2"/><circle cx="142" cy="137" r="2"/><circle cx="152" cy="137" r="2"/><circle cx="162" cy="137" r="2"/><circle cx="172" cy="137" r="2"/><circle cx="182" cy="137" r="2"/></g><!-- RDL region with fan traces --><rect x="38" y="144" width="186" height="36" rx="2" fill="#14202b" stroke="#30363d"/><text x="131" y="165" text-anchor="middle" fill="#586b7a" font-size="8.5">RDL</text><g stroke="#b8732e" stroke-width="1.3" fill="none"><line x1="77" y1="144" x2="52" y2="180"/><line x1="97" y1="144" x2="82" y2="180"/><line x1="117" y1="144" x2="110" y2="180"/><line x1="137" y1="144" x2="140" y2="180"/><line x1="160" y1="144" x2="170" y2="180"/><line x1="180" y1="144" x2="200" y2="180"/></g><!-- coarse balls --><g fill="#e0b13a"><circle cx="52" cy="185" r="4"/><circle cx="82" cy="185" r="4"/><circle cx="110" cy="185" r="4"/><circle cx="140" cy="185" r="4"/><circle cx="170" cy="185" r="4"/><circle cx="200" cy="185" r="4"/></g><text x="126" y="202" text-anchor="middle" fill="#8b949e" font-size="8.5">coarse ball pitch</text><text x="36" y="224" fill="#adb5bd" font-size="11">RDL turns tight die-pad pitch into</text><text x="36" y="239" fill="#adb5bd" font-size="11">board-friendly ball pitch —</text><text x="36" y="264" fill="#38bdf8" font-size="11" font-weight="700">and fans I/O past the die edge.</text><text x="36" y="289" fill="#8b949e" font-size="10.5">~10–40 µm pads in →</text><text x="36" y="304" fill="#8b949e" font-size="10.5">~100–500 µm balls out.</text><text x="36" y="329" fill="#8b949e" font-size="10.5">The enabling interconnect for</text><text x="36" y="343" fill="#8b949e" font-size="10.5">WLCSP, fan-out and chiplets.</text><!-- ===== PANEL 2 ===== --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="283" y="92" fill="#38bdf8" font-size="14" font-weight="700">2 · The copper/polymer stack</text><text x="330" y="110" fill="#adb5bd" font-size="8">die pad</text><rect x="312" y="112" width="14" height="8" fill="#b8732e"/><!-- polymer block --><rect x="300" y="118" width="140" height="80" rx="2" fill="#241a12" stroke="#5a4632"/><!-- M1 --><rect x="308" y="132" width="66" height="6" fill="#b8732e"/><text x="310" y="130" fill="#f0d9b5" font-size="8">M1</text><rect x="368" y="132" width="6" height="20" fill="#d08a4a"/><!-- M2 --><rect x="360" y="150" width="66" height="6" fill="#b8732e"/><text x="362" y="148" fill="#f0d9b5" font-size="8">M2</text><rect x="418" y="150" width="6" height="22" fill="#d08a4a"/><!-- M3 --><rect x="336" y="170" width="88" height="6" fill="#b8732e"/><text x="338" y="168" fill="#f0d9b5" font-size="8">M3</text><rect x="360" y="176" width="6" height="18" fill="#d08a4a"/><text x="384" y="146" fill="#9fd8ef" font-size="8">via</text><!-- UBM + ball --><rect x="354" y="192" width="18" height="5" fill="#586069"/><circle cx="363" cy="203" r="6" fill="#e0b13a"/><text x="376" y="206" fill="#adb5bd" font-size="8">UBM + ball</text><text x="283" y="226" fill="#c9d1d9" font-size="10.5">3–4 copper layers in polymer;</text><text x="283" y="241" fill="#c9d1d9" font-size="10.5">vias step signals between them.</text><text x="283" y="264" fill="#c4b5fd" font-size="10.5">PI: Dk ~3.5   ·   PBO: Dk ~2.6</text><text x="283" y="285" fill="#adb5bd" font-size="10.5">Line/space scales from</text><text x="283" y="300" fill="#adb5bd" font-size="10.5">10/10 µm down to 2/2 µm.</text><text x="283" y="325" fill="#8b949e" font-size="10.5">Finer L/S → more routing per</text><text x="283" y="339" fill="#8b949e" font-size="10.5">layer, but harder to yield.</text><!-- ===== PANEL 3 ===== --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="530" y="92" fill="#38bdf8" font-size="14" font-weight="700">3 · Building it &amp; the knobs</text><g font-size="9.5" font-weight="700" fill="#0d1117"><circle cx="537" cy="112" r="6.5" fill="#38bdf8"/><text x="537" y="115" text-anchor="middle">1</text><circle cx="537" cy="132" r="6.5" fill="#38bdf8"/><text x="537" y="135" text-anchor="middle">2</text><circle cx="537" cy="152" r="6.5" fill="#38bdf8"/><text x="537" y="155" text-anchor="middle">3</text><circle cx="537" cy="172" r="6.5" fill="#38bdf8"/><text x="537" y="175" text-anchor="middle">4</text><circle cx="537" cy="192" r="6.5" fill="#38bdf8"/><text x="537" y="195" text-anchor="middle">5</text></g><text x="549" y="115" fill="#c9d1d9" font-size="10">Spin-coat polymer, bake, cure</text><text x="549" y="135" fill="#c9d1d9" font-size="10">Open vias — laser or litho</text><text x="549" y="155" fill="#c9d1d9" font-size="10">Sputter a copper seed layer</text><text x="549" y="175" fill="#c9d1d9" font-size="10">Electroplate Cu, pattern, etch</text><text x="549" y="195" fill="#c9d1d9" font-size="10">Repeat per layer (2–8 layers)</text><line x1="530" y1="208" x2="724" y2="208" stroke="#30363d"/><text x="530" y="228" fill="#e0b13a" font-size="11.5" font-weight="700">The hard parts</text><g fill="#e0b13a"><circle cx="534" cy="241" r="2.6"/><circle cx="534" cy="256" r="2.6"/><circle cx="534" cy="271" r="2.6"/><circle cx="534" cy="286" r="2.6"/></g><text x="544" y="244" fill="#adb5bd" font-size="10.5">layer-to-layer overlay/alignment</text><text x="544" y="259" fill="#adb5bd" font-size="10.5">fine L/S yield (down to 2/2 µm)</text><text x="544" y="274" fill="#adb5bd" font-size="10.5">copper plating uniformity</text><text x="544" y="289" fill="#adb5bd" font-size="10.5">polymer-cure stress → warpage</text><text x="530" y="315" fill="#f87171" font-size="10.5" font-weight="700">Overlay and plating set how tight</text><text x="530" y="329" fill="#f87171" font-size="10.5" font-weight="700">the RDL can be pushed.</text><!-- ===== BOTTOM CARDS ===== --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="36" y="406" fill="#38bdf8" font-size="12.5" font-weight="700">Pitch translator</text><text x="36" y="424" fill="#adb5bd" font-size="10">Converts µm-pitch die bumps into</text><text x="36" y="437" fill="#adb5bd" font-size="10">board-friendly ball pitch and fans</text><text x="36" y="450" fill="#adb5bd" font-size="10">I/O past the die edge.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="283" y="406" fill="#c4b5fd" font-size="12.5" font-weight="700">Copper on polymer</text><text x="283" y="424" fill="#adb5bd" font-size="10">Plated copper traces sit in spin-</text><text x="283" y="437" fill="#adb5bd" font-size="10">coated PI/PBO; stack 2–8 layers</text><text x="283" y="450" fill="#adb5bd" font-size="10">with vias between them.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="530" y="406" fill="#e0b13a" font-size="12.5" font-weight="700">Alignment &amp; plating gate yield</text><text x="530" y="424" fill="#adb5bd" font-size="10">Layer overlay, fine line/space and</text><text x="530" y="437" fill="#adb5bd" font-size="10">copper plating uniformity set how</text><text x="530" y="450" fill="#adb5bd" font-size="10">tight RDL can go.</text></svg>

Redistribution Layer (RDL) is the thin-film metal interconnect structure that reroutes I/O from chip pads to package bumps or between die in advanced packages — achieving 2/2μm to 10/10μm line/space, 2-10 metal layers, <1Ω/mm resistance, enabling fan-out packaging, 2.5D interposers, and heterogeneous integration with 500-5000 I/O connections at 0.15-0.5mm pitch for applications from mobile processors to AI accelerators.

RDL Structure and Materials:

• Metal Layers: Cu electroplating most common; 2-10 layers typical; thickness 2-10μm per layer; seed layer Ti/Cu or Ta/Cu by sputtering; photolithography for patterning
• Dielectric Layers: polyimide (PI) or polybenzoxazole (PBO) between metal layers; spin-coat or laminate; thickness 5-15μm; dielectric constant 2.8-3.5; low CTE (<30 ppm/°C) for reliability
• Via Formation: photolithography or laser drilling; via diameter 10-50μm; aspect ratio 1:1 to 2:1; Cu fill by electroplating; connects metal layers
• Passivation: final protective layer; polyimide or solder resist; thickness 5-20μm; openings for bump pads; protects RDL from environment

RDL Fabrication Processes:

• Semi-Additive Process (SAP): sputter thin seed layer (0.1-0.5μm); photolithography defines pattern; electroplate Cu (2-10μm); strip resist; etch seed layer; fine-line capability (2/2μm)
• Subtractive Process: sputter or electroplate thick Cu (5-15μm); photolithography; wet or dry etch Cu; coarser lines (10/10μm); simpler but less precise
• Dual Damascene: deposit dielectric; etch trenches and vias; fill with Cu; CMP planarization; borrowed from BEOL; used for finest pitch (<2μm)
• Process Selection: SAP for fine-line (<5μm); subtractive for coarse-line (>10μm); dual damascene for ultra-fine (<2μm); cost-performance trade-off

Line Width and Pitch Scaling:

• Coarse RDL: 10/10μm line/space; used in standard FOWLP, WLP; i-line lithography (365nm); mature process; low cost
• Fine RDL: 2/2μm to 5/5μm line/space; used in advanced FOWLP, 2.5D interposers; KrF lithography (248nm); higher cost but enables higher density
• Ultra-Fine RDL: <2/2μm line/space; research and development; ArF lithography (193nm) or EUV; for future ultra-high-density packages
• Scaling Trend: moving from 10μm to 2μm over past decade; driven by I/O density requirements; 1μm target for next generation

Electrical Performance:

• Resistance: 2-5μm thick Cu; sheet resistance 3-10 mΩ/sq; line resistance 0.5-2Ω/mm depending on width; lower than PCB traces (5-20Ω/mm)
• Capacitance: dielectric k=2.8-3.5; line-to-line capacitance 0.1-0.5 pF/mm; lower than on-chip interconnect (k=3-4); suitable for high-speed signals
• Inductance: 0.5-2 nH/mm depending on geometry; lower than wire bonds (1-5 nH/mm); enables multi-Gb/s signaling
• Signal Integrity: low R, L, C enable clean signal transmission; suitable for DDR, PCIe, USB, high-speed interfaces; simulation and optimization critical

Applications by Package Type:

• FOWLP: 2-6 RDL layers; 2/2μm to 10/10μm line/space; fan-out area for I/O redistribution; enables 500-2000 I/O; used in mobile processors, AI edge chips
• 2.5D Interposer: 2-4 RDL layers on silicon; 0.4/0.4μm to 2/2μm line/space; ultra-high density; connects HBM to logic; bandwidth >1 TB/s
• Panel-Level Packaging: RDL on large panels (510×515mm); 5/5μm to 10/10μm typical; cost-effective for high volume; used in consumer, IoT
• Chip-on-Wafer (CoW): RDL on wafer before die attach; adaptive patterning compensates die placement variation; used in some FOWLP variants

Design and Routing:

• Design Rules: minimum line width, space, via size; design rule manual (DRM) from package house; typically 2-10× coarser than on-chip
• Routing Density: 50-200 wires per mm depending on pitch; sufficient for most applications; bottleneck is bump pitch, not RDL routing
• Power Distribution: dedicated power/ground planes or mesh; IR drop analysis critical; <50mV drop target; wide traces for low resistance
• Signal Integrity: impedance control (50Ω single-ended, 100Ω differential); length matching for high-speed buses; simulation with 3D EM tools

Manufacturing Challenges:

• Overlay: multi-layer RDL requires tight overlay; ±2-5μm depending on pitch; stepper alignment critical; warpage affects overlay
• Uniformity: Cu thickness uniformity ±10% across wafer/panel; affects resistance and impedance; plating optimization critical
• Defects: particles, scratches, opens, shorts; <0.1 defects/cm² target; cleanroom environment, process control essential
• Yield: RDL yield 95-98% typical; lower for fine-line; improving with process maturity; defects main yield detractor

Equipment and Suppliers:

• Lithography: Canon, Nikon i-line or KrF steppers; overlay ±1-3μm; throughput 50-100 wafers/hour; older generation tools cost-effective
• Plating: Ebara, Atotech, Technic for Cu electroplating; automated plating lines; thickness uniformity ±5-10%; throughput 100-200 wafers/hour
• Metrology: KLA, Onto Innovation for overlay, CD, film thickness; inline monitoring; critical for multi-layer RDL
• Materials: DuPont, HD MicroSystems, Fujifilm for polyimide; Rohm and Haas for photoresist; continuous development for finer pitch

Cost and Economics:

• Process Cost: $10-50 per wafer per RDL layer depending on pitch; fine-line more expensive; 2-6 layers typical; total RDL cost $50-300 per wafer
• Yield Impact: RDL defects reduce package yield by 2-5%; offset by functionality and performance benefits
• Value Proposition: enables high I/O density, heterogeneous integration; critical for advanced packages; cost justified by system-level benefits
• Market Size: RDL materials and equipment market $2-3B annually; growing 10-15% per year; driven by advanced packaging adoption

Future Trends:

• Finer Pitch: 1/1μm line/space for ultra-high density; requires ArF or EUV lithography; enables >5000 I/O packages
• Thicker Metal: 10-20μm Cu for low-resistance power delivery; challenges in patterning and stress; required for high-power devices
• New Materials: exploring Ru, Co for lower resistance; alternative dielectrics for lower k; improving performance
• Hybrid Processes: combine RDL with hybrid bonding; ultra-high bandwidth (>2 TB/s); next-generation heterogeneous integration

Redistribution Layer is the critical interconnect technology that enables advanced packaging — by providing flexible, high-density metal routing at package level, RDL enables fan-out packaging, 2.5D integration, and heterogeneous die integration with 500-5000 I/O connections, forming the foundation of modern advanced packaging that powers everything from smartphones to AI supercomputers.