Semiconductor Reliability Engineering is the discipline that ensures integrated circuits maintain their specified performance over the required operational lifetime (typically 10-25 years) by characterizing, modeling, and mitigating wear-out mechanisms — electromigration, hot carrier injection, bias temperature instability, and gate oxide breakdown — that progressively degrade transistor and interconnect parameters, where reliability qualification requires accelerated stress testing that compresses years of field operation into weeks of lab testing.

Key Wear-Out Mechanisms

• Electromigration (EM): High current density in copper interconnects causes Cu atom migration along grain boundaries in the direction of electron flow. Atoms accumulate at one end (hillock), creating a void at the other — eventually causing open-circuit failure. Governed by Black's equation: MTTF ∝ J⁻² × exp(Ea/kT), where J is current density and Ea is activation energy (~0.7-0.9 eV for Cu). Design rules limit current density to <1-2 MA/cm² depending on wire width and temperature.

• Hot Carrier Injection (HCI): High-energy (hot) electrons near the drain of a MOSFET gain enough energy to be injected into the gate oxide, where they become trapped. This shifts the threshold voltage and degrades transconductance over time. Worst at low temperature (higher mobility → higher carrier energy). Mitigated by lightly-doped drain (LDD) structures and reduced supply voltage.

• Bias Temperature Instability (BTI):
• NBTI (Negative BTI): Occurs in pMOS under negative gate bias at elevated temperature. Interface traps and oxide charges accumulate, shifting Vth positively (|Vth| increases). Partially recovers when stress is removed. The dominant reliability concern for CMOS logic at advanced nodes.
• PBTI (Positive BTI): Occurs in nMOS with high-k dielectrics under positive gate bias. Electron trapping in the high-k layer shifts Vth.

• Time-Dependent Dielectric Breakdown (TDDB): The gate oxide progressively degrades under electric field stress. Trap-assisted tunneling creates a percolation path through the oxide, leading to sudden breakdown (hard BD) or gradual tunneling increase (soft BD). Thinner oxide at each node increases the field, accelerating TDDB. Oxide thickness must maintain <100 FIT (failures in time) at operating conditions over the product lifetime.

Accelerated Life Testing

Reliability tests use elevated stress (voltage, temperature, current) to accelerate wear-out:

• HTOL (High Temperature Operating Life): 125°C, 1.1×VDD, 1000 hours. Accelerates BTI, HCI, and oxide degradation.
• EM Testing: 300°C, high current density, 196-500 hours. Extrapolate to operating temperature using Black's equation.
• ESD Testing: Human Body Model (HBM), Charged Device Model (CDM) pulse testing per JEDEC/ESDA standards.

Reliability Budgeting

Total degradation budget is allocated across all mechanisms: e.g., ΔVth < 50 mV over 10 years = 20 mV for BTI + 15 mV for HCI + 15 mV margin. Design tools (aging simulators: Synopsys MOSRA, Cadence RelXpert) simulate lifetime degradation and verify that timing margins survive the specified lifetime.

Semiconductor Reliability Engineering is the assurance discipline that guarantees today's chip will still function a decade from now — predicting and preventing the atomic-scale degradation mechanisms that slowly erode device performance over billions of operating hours.