Resist Spin Coating is the process of applying a thin, uniform layer of photoresist onto a silicon wafer by dispensing liquid resist onto the rotating wafer surface, allowing centrifugal force to spread the resist uniformly across the wafer before it sets into a solid film through solvent evaporation. One of the most critical steps in photolithography, spin coating uniformity directly determines critical dimension (CD) uniformity across the wafer — non-uniformity in resist thickness translates directly into dose variation, dimensional errors, and yield loss.

The Spin Coating Process Sequence

Step 1: Wafer Pre-treatment (HMDS Priming)

Before resist coating, bare silicon oxide surfaces are treated with Hexamethyldisilazane (HMDS) to improve resist adhesion:

• HMDS replaces hydrophilic Si-OH groups with hydrophobic Si-O-Si(CH₃)₃ groups
• Without HMDS, water-based developers can undercut the resist at adhesion failure points
• HMDS is applied by vapor prime (preferred) or spin coat
• Temperature: 90-150°C for 60-120 seconds in vapor prime oven
• Wafers must reach ambient temperature before resist coating

Step 2: Resist Dispense

• Wafer is held by vacuum chuck and rotated at low speed (500-1000 RPM) during dispense
• Conventional dispense: Nozzle delivers 1-3 mL of resist to wafer center
• Dynamic dispense: Resist dispensed during low-speed spin to pre-spread before high-speed
• Static dispense: Resist dispensed onto stationary wafer, then spin starts
• Amount dispensed: Excess ensures full coverage but wastes expensive resist
• EUV resists are particularly expensive (>$10,000/liter) — minimal dispense volume is required

Step 3: Spin-Up and Film Formation

The core physics of spin coating:

• Rapid acceleration to target spin speed (e.g., 2000-6000 RPM)
• Centrifugal force drives resist from center outward toward edge
• Viscous shear forces between resist layers create radial flow
• 70-80% of resist is flung off the wafer — only a thin film remains
• Solvent evaporates during spinning, increasing viscosity and eventually stopping flow
• Final film thickness freezes when viscosity becomes too high to flow

Spin Coating Film Thickness Control

Film thickness $t$ follows the empirical relationship:

$$t \propto \frac{\eta^\alpha C^\beta}{\omega^\gamma}$$

where $\eta$ = resist viscosity, $C$ = solid concentration, $\omega$ = angular velocity (RPM), and empirical exponents typically $\alpha \approx 0.5$, $\beta \approx 2$, $\gamma \approx 0.5$.

Practical thickness control levers:

Target thickness: 10-200 nm for advanced nodes (EUV); 100-500 nm for older nodes.

Step 4: Soft Bake (Post-Apply Bake)

After spin coating, the wafer is baked on a precision hotplate:

• Temperature: 90-130°C for 60-90 seconds
• Purpose: Evaporate residual solvent (reduces from ~20% to <5%)
• Effect: Improves resist uniformity, reduces standing wave effects from residual solvent
• Critical: Temperature uniformity ±0.5°C across hotplate required for CD uniformity
• Too hot: Initiates premature photoacid generation (chemically amplified resists)
• Too cool: Residual solvent causes poor contrast and CD errors

Step 5: Edge Bead Removal (EBR)

Spin coating creates a thicker bead of resist at the wafer edge:

• Edge bead is 2-5x thicker than center film
• Causes focus errors if wafer is supported at edge during exposure
• EBR: Solvent dispensed at wafer edge while spinning dissolves edge bead
• Typical EBR width: 2-5 mm from edge
• Backside bead removal also required — resist must not contaminate chuck systems

Track Systems: Integrated Coat-Develop Platforms

Modern fabs use automated track systems that integrate:

• Atmospheric and vacuum wafer transfer
• HMDS prime oven
• Spin coat modules (2-8 per track)
• Bake plates (soft bake, post-exposure bake, hard bake)
• Develop modules (puddle develop for 193nm/EUV)
• Chill plates for temperature stabilization

Leading track vendors:

• TEL (Tokyo Electron): CLEAN TRACK Lithius series — market leader, integrated with ASML scanners
• Screen Semiconductor Solutions: SK-Series, common in memory fabs
• SEMES: Samsung subsidiary, used in Samsung Foundry fabs

A single 300mm track processes 100-200 wafers per hour through the full coat-develop sequence.

Uniformity Specifications

• Film thickness uniformity (3σ): ±0.3-1.0% for standard resists
• Within-wafer uniformity: ±0.5 nm for EUV thicknesses (~30 nm)
• Wafer-to-wafer repeatability: ±0.3% 3σ
• Long-term drift: Monitored by metrology wafers every 25-50 production wafers

Challenges at Advanced Nodes

• EUV resist thickness: Target 20-40 nm (vs 100+ nm for 193nm) — extreme precision required
• Metal oxide resists (MOR): Higher resolution but different rheology, requires process re-optimization
• Void formation: Air bubbles in dispense lines cause coating defects — requires bubble-free delivery systems
• Resist cost: EUV resists at $10K-$20K/liter make waste reduction critical
• Outgassing: EUV resist absorbers can outgas and contaminate the EUV mask (reticle) — strict volatile organic compound (VOC) limits

Resist spin coating is performed on every wafer through the lithographic process — at 3nm, a wafer may cycle through 80+ lithography layers, each requiring precise coat, bake, expose, and develop.