Resist stripping — commonly called ashing when performed with oxygen plasma — is the process of completely removing photoresist from a wafer after it has served its patterning purpose during lithography and etch or implantation. Every wafer in a modern fab passes through at least one strip step per masking layer, making ashing one of the highest-volume unit operations in semiconductor manufacturing. At advanced nodes below 7 nm, where a single mask set can exceed 80 layers, cumulative strip-induced damage to gate dielectrics, low-$k$ interconnect films, and silicide contacts becomes a first-order yield limiter. The fundamental chemistry is deceptively simple — atomic oxygen reacts with carbon-based resist to form volatile CO$_2$ and H$_2$O — but the engineering challenge is controlling ion energy, radical flux uniformity, and post-strip residue levels to satisfy damage budgets that tighten with every technology generation. TSMC, Samsung, Intel, and GlobalFoundries each maintain proprietary strip recipes that balance throughput against damage, with the downstream microwave asher emerging as the workhorse tool because it delivers radical-dominated stripping with minimal ion bombardment.

Oxygen-radical stripping follows Arrhenius kinetics with an activation energy of 0.3 eV for standard photoresist, yielding a strip rate of 450.8 nm/min at 250 °C on a downstream asher. The rate equation $R = A \exp(-E_a / k_B T)$ captures the exponential temperature dependence: raising the platen from 150 °C to 300 °C increases the strip rate by roughly an order of magnitude. Atomic oxygen generated by microwave dissociation of O$_2$ at 2.45 GHz diffuses downstream through a quartz tube to the wafer surface, where it abstracts hydrogen and breaks C–C backbone bonds in the resist polymer. The volatile products — primarily CO$_2$, CO, and H$_2$O — are pumped away at pressures of 1–3 Torr. Because the downstream geometry separates the plasma generation zone from the wafer, ion energies at the wafer surface remain below 2 eV, far below the 5 eV threshold for gate-oxide damage at 3 nm nodes. Applied Materials, Lam Research, and Mattson Technology (now Beijing E-Town) supply the dominant downstream asher platforms — the Producer, Gamma, and Suprema families respectively — each optimized for radical transport efficiency of approximately 72.0% from source to wafer.

Ion-implanted resist develops a carbonized surface crust with an effective activation energy of 0.55 eV, reducing the O$_2$ strip rate by a factor of 256.08× and forcing multi-step strip sequences. When photoresist is exposed to implant doses above approximately 5 × 10$^{14}$ cm$^{-2}$, the top 50–200 nm forms an amorphous carbon crust that is nearly impervious to atomic oxygen. At 250 °C the crust strips at only 1.8 nm/min compared with 450.8 nm/min for unimplanted resist. The standard mitigation is a two- or three-step process: a brief O$_2$/CF$_4$ (5%) plasma to crack the crust by fluorine attack on the carbonized surface, followed by a high-flow O$_2$ bulk strip, and optionally a final N$_2$/H$_2$ forming-gas step to reduce any metal oxides formed during the oxygen exposure. Samsung and TSMC specify crust-break recipes with CF$_4$ additions limited to 3–7% to avoid fluorine contamination of the underlying silicon, while Intel's advanced nodes use a proprietary Ar/O$_2$ sputtering pre-step to physically ablate the crust before chemical stripping.

Strip chemistry selection trades off removal rate against substrate damage: pure O$_2$ plasma provides the highest rate at 450.8 nm/min but risks metal oxidation, while N$_2$/H$_2$ forming gas runs at 99.7 nm/min with zero oxidation risk. The choice of strip gas determines not only the etch rate but also the chemical state of exposed metal surfaces. In copper dual-damascene back-end-of-line processing, any oxygen exposure converts the copper surface to CuO, increasing via resistance by 10–30%. N$_2$/H$_2$ forming-gas plasmas eliminate this risk by providing reducing chemistry that strips resist while simultaneously removing native copper oxides. The trade-off is a lower activation energy modifier of 1.15× and a rate multiplier of only 0.6×, resulting in strip times 4–5× longer than pure O$_2$. For BEOL processing at 28 nm and below, Synopsys process models and Applied Materials recipe libraries both recommend forming-gas strip as the baseline, with O$_2$ reserved for front-end-of-line steps where copper is not exposed.

Downstream microwave ashers achieve ±1.8% strip uniformity at 100 wafers per hour, displacing barrel ashers that suffer ±8.0% non-uniformity from batch-loading geometry. The evolution of strip equipment mirrors the semiconductor industry's transition from batch to single-wafer processing. Barrel ashers, which load 25–50 wafers into a quartz tube surrounded by an RF coil, dominated through the 250 nm era but cannot meet the ±3% within-wafer uniformity required at 65 nm and below. Single-wafer downstream ashers place the microwave plasma source above the wafer and transport radicals through a showerhead, achieving ±1.8% uniformity with precise temperature control at each wafer position. ICP-source downstream ashers — offered by Lam Research as the Gamma G400 and by Screen as the WS-series — push throughput to 100 wafers per hour by using dual-chamber configurations with shared load-lock modules. Mattson Technology's Suprema platform achieves comparable throughput using a proprietary remote plasma source with a toroidal chamber geometry that maximizes radical generation efficiency. Google Cloud's semiconductor process modeling team and Cadence Spectre-based reliability simulators both incorporate strip damage models calibrated against downstream asher ion-energy distributions.

At the 3 nm node, strip-induced gate-oxide damage limits maximum ion energy to 5 eV and antenna ratios to 2.1, forcing exclusive use of remote-plasma strip tools for all gate-first integration flows. Plasma charging damage during ashing manifests as Fowler-Nordheim tunneling current through the gate oxide, driven by antenna-effect charge collection on interconnect metal connected to the gate. The damage scales with the product of ion energy, plasma density, and exposure time, normalized by gate oxide thickness:

where $J_{ion}$ is the ion current density, $E_{ion}$ the ion energy, $t_{strip}$ the strip duration, $t_{ox}$ the gate oxide thickness, and $AR$ the antenna ratio. At 180 nm with a 4.0 nm gate oxide, antenna ratios up to 100.0 are tolerable; at 3 nm with a 0.3 nm equivalent oxide thickness, the limit drops to 2.1. ARM and Qualcomm standard-cell libraries for sub-5 nm nodes include antenna-rule-aware routing constraints that account for strip-induced charging, and Apple's A-series and M-series chip designs incorporate dummy metal fills specifically to reduce local antenna ratios during strip steps. MediaTek's Dimensity platform team reports that switching from RIE strip to downstream ashing reduced IDDQ outlier rates by 40% at their 4 nm node.

Post-etch polymer residues containing fluorinated carbon, sputtered metal, and re-deposited etch byproducts require dedicated post-strip cleaning with EKC or ST-250 solvent formulations that dissolve organometallic complexes without attacking exposed copper or low-$k$ dielectrics. Ashing alone removes the bulk photoresist but leaves behind a 1–5 nm residue layer composed of fluorocarbon polymers (from fluorine-based etch chemistries), sputtered metal atoms, and silicon-containing etch byproducts. These residues, if not removed, cause via resistance increases of 20–50% and adhesion failures in subsequent metal deposition. The industry-standard approach combines dry ashing with a wet solvent clean: DuPont's EKC265 and Entegris's ST-250 are the dominant formulations, using amine-based chemistry to chelate metal residues while maintaining compatibility with Cu and low-$k$ CDO (carbon-doped oxide) films. Verification of complete residue removal uses XPS (X-ray photoelectron spectroscopy) to confirm carbon concentration below 0.5 atomic percent and fluorine below 0.1 atomic percent on the stripped surface. IEEE and SEMI standards specify strip completeness criteria in SEMI E142 and IEEE 1620, which define maximum allowable residual contamination levels for each technology node.

The shift to EUV resist at sub-3 nm nodes introduces metal-oxide-based inorganic resists that cannot be ashed by conventional O$_2$ plasma, driving development of HCl/Cl$_2$ dry-etch strip chemistries and plasma-free vapor-phase removal processes. EUV metal-oxide resists — based on tin-oxide, hafnium-oxide, or zirconium-oxide nanoparticle films from Inpria (now JSR Micro) — do not contain the carbon backbone that makes conventional CARs (chemically amplified resists) amenable to oxygen ashing. Instead, these inorganic films require halogen-based chemistry: HCl vapor at 200–350 °C converts SnO$_x$ resist to volatile SnCl$_4$ ($T_{boil}$ = 114 °C), while Cl$_2$ plasma can etch HfO$_x$ and ZrO$_x$ at controlled rates. Lam Research and Tokyo Electron (TEL) are developing dedicated metal-oxide resist strip modules, and Ansys process simulation tools now include SnCl$_4$-based strip kinetics in their etch modeling suite. The transition from organic to inorganic resist strip represents the most significant change in ashing technology since the shift from barrel to downstream processing in the 1990s, and will require entirely new endpoint detection, exhaust treatment, and tin-abatement systems in the fab exhaust infrastructure.

Read resist strip / ashing through a process-integration lens and the apparent simplicity of burning off photoresist dissolves into a multi-variable optimization spanning radical kinetics, charging-damage budgets, organometallic residue chemistry, and equipment throughput economics. Each technology node tightens the damage envelope while adding masking layers that multiply cumulative strip exposure, and the emerging shift to inorganic EUV resists promises to rewrite the chemistry entirely — transforming ashing from a mature commodity process into an active frontier of semiconductor equipment and materials innovation.