Retargeting is a model-based computational lithography process that modifies design polygon shapes with corrections including biases, serifs, hammerheads, and sub-resolution assist features before mask writing, compensating for systematic optical, resist, and etch distortions that would otherwise cause the printed wafer pattern to deviate from design intent — the critical pre-tapeout optimization step that transforms an ideal design layout into a manufacturable mask dataset.
What Is Retargeting?
- Definition: The systematic modification of design polygons to pre-compensate for predictable optical proximity effects, resist chemistry, and etch loading that will distort the final printed pattern — ensuring the silicon result matches design intent within specified tolerances.
- Scope: Retargeting encompasses Optical Proximity Correction (OPC), Sub-Resolution Assist Features (SRAFs), and Source-Mask Optimization (SMO) — the full computational lithography flow that converts design GDS to mask GDS.
- Forward vs. Inverse Problem: Lithography simulation predicts printed patterns from mask shapes (forward problem); retargeting solves the inverse — what mask shapes produce the desired printed pattern given the known process distortions?
- Model-Based Correction: Process models calibrated against measured silicon data predict how each mask shape prints across focus and exposure variations, enabling accurate correction before any silicon is processed.
Why Retargeting Matters
- Pattern Fidelity: Without OPC, corner rounding, line shortening, and density-dependent CD variation would make most sub-250nm designs non-functional in silicon.
- Process Window: Correctly placed SRAFs improve depth of focus and exposure latitude by 20-50%, dramatically improving manufacturing yield across the focus-exposure matrix.
- Yield and Reliability: Uncorrected patterns produce systematic defects (bridging, open circuits) that appear in every die of every wafer — retargeting prevents whole-lot yield loss.
- Mask Complexity: Modern OPC adds millions of correction vertices to a layout; retargeted mask GDS files are 10-100× larger than the original design GDS.
- Tapeout Gatekeeping: OPC verification (simulating the corrected mask) must confirm corrections are effective before committing to $500K-5M mask set fabrication.
Retargeting Techniques
Optical Proximity Correction (OPC):
- Rule-Based OPC: Apply fixed biases and serifs based on feature width and pitch lookup tables — fast but limited accuracy for complex layouts.
- Model-Based OPC: Iterative simulation-correction loop converges to mask shapes that minimize edge placement error (EPE) between simulated and target patterns.
- Inverse Lithography Technology (ILT): Full inverse optimization of mask shapes without polygon constraints — produces curvilinear masks with optimal process window for each specific pattern.
Sub-Resolution Assist Features (SRAFs):
- Non-printing features placed adjacent to isolated main features to make them behave optically like dense features.
- Improve isolated-to-dense process window matching by 30-50% — critical for uniform CD across variable density layouts.
- Placement rules derived from optical simulation models or full ILT co-optimization.
Source-Mask Co-Optimization (SMO):
- Simultaneously optimize illumination source shape AND mask pattern for maximum process window.
- Provides best achievable process window but computationally intensive — requires GPU acceleration.
- Full-chip SMO requires days of compute time; typically applied to most critical layers only.
Retargeting Quality Metrics
| Metric | Description | Target (Advanced Nodes) |
|--------|-------------|------------------------|
| EPE (Edge Placement Error) | Deviation of printed edge from target | < 1nm |
| Process Window | Focus/exposure range for spec compliance | > ±10% exposure, > ±30nm focus |
| MEEF | Mask error amplification factor | < 3 isolated, < 2 dense |
| Run Time | Full-chip OPC computation | Hours to days |
Retargeting is the computational bridge between idealized design intent and manufacturable silicon reality — transforming clean design geometries into precisely engineered mask patterns that account for the optical, chemical, and physical distortions of the lithographic process, enabling the sub-10nm feature accuracy that makes modern semiconductor devices possible.