Routing Congestion is the condition where a region of the chip has insufficient routing resources to accommodate all required wire connections — causing routing tools to fail, requiring detours that increase delay, or resulting in DRC violations at tapeout.

What Is Routing Congestion?

• Each metal layer has a finite number of routing tracks per unit area.
• Track density = available tracks / required connections at each grid tile.
• Congestion: Required tracks > available tracks in a tile → overflow.
• GRC (Global Routing Congestion): Estimated during placement; directs placement engine.
• Detail routing overflow: Actual DRC violations when router cannot resolve congestion.

Congestion Metrics

• Overflow: Number of connections that cannot be routed on preferred layer.
• Worst Congestion Layer: Metal layer with highest overflow rate.
• Congestion Heatmap: Visualization of overflow density across die — hot spots require attention.

Root Causes

• High local cell density: Too many cells packed in small area → many nets must cross through.
• High-fanout nets: One net branches to many sinks → many wires in one area.
• Wide buses: 64 or 128-bit buses bundle many connections through chokepoints.
• Hard macro placement: Macros (SRAMs, IPs) block routing channels.
• Low utilization estimate: Floor plan too small for actual routing demand.

Congestion Fixing Strategies

• Floorplan adjustment: Spread cells, resize blocks, move macros to open routing channels.
• Cell spreading: Reduce local cell density by spreading utilization.
• Buffer insertion: Break long routes by inserting repeaters at intermediate points.
• Layer assignment: Route critical high-density nets on less congested layers.
• Via minimization: Fewer vias → more routing track availability.
• NDR (Non-Default Rule) nets: Route sensitive nets with wider spacing → consumes more tracks but reduces coupling noise.

Congestion-Driven Placement

• Modern P&R tools run global routing estimation during placement.
• Placement engine moves cells to flatten congestion heatmap proactively.
• Congestion-driven vs. timing-driven: Tension between where timing wants cells and where congestion allows them.

Routing congestion is one of the primary physical design challenges in tapeout — a chip with unresolved congestion cannot be routed to DRC-clean completion, making congestion analysis and mitigation essential from early floorplan through final signoff.