Rapid Thermal Processing (RTP) Spike Anneal and Millisecond Anneal is the application of ultra-short, high-temperature thermal treatments to activate implanted dopants and repair lattice damage while stringently limiting thermal diffusion to preserve nanometer-scale junction profiles — as CMOS technology scales, the thermal budget available for dopant activation shrinks because diffusion lengths must be kept below a few nanometers, driving the evolution from conventional furnace anneals to spike RTP, flash lamp, and laser millisecond anneal techniques.
Spike Anneal Fundamentals: Spike RTP uses tungsten-halogen lamp arrays to heat wafers at ramp rates of 150-400 degrees Celsius per second to peak temperatures of 1000-1100 degrees Celsius, with near-zero dwell time at the peak. The wafer is held at the peak for less than one second before rapid cooldown. The brief thermal exposure achieves high dopant activation (sheet resistance reduction) while minimizing lateral and vertical diffusion. Temperature uniformity across the wafer is maintained within plus or minus 2 degrees Celsius through multi-zone lamp control and closed-loop pyrometric feedback. Edge ring design and gas flow optimization prevent temperature overshoot at the wafer periphery.
Millisecond Anneal Technologies: For sub-20 nm nodes, even spike anneal provides excessive thermal budget. Flash lamp anneal uses high-intensity xenon arc lamps to heat only the wafer surface to 1200-1350 degrees Celsius for 0.1-10 milliseconds while the wafer bulk remains at a lower intermediate temperature (typically 400-800 degrees Celsius set by a pre-heat stage). This surface-dominated heating achieves very high dopant activation with virtually zero diffusion. Laser spike anneal (LSA) uses a scanned CO2 laser line beam (typically 10.6 micron wavelength) to heat a narrow strip of the wafer surface to peak temperatures exceeding 1250 degrees Celsius for dwell times of 0.1-1 millisecond. The wafer is scanned line by line to cover the entire surface.
Temperature Measurement Challenges: At millisecond timescales, conventional thermocouple and pyrometer measurements are too slow. Specialized high-speed pyrometers with sub-millisecond response times are required. Emissivity variations from pattern density differences across the die create apparent temperature non-uniformities. Advanced systems use multi-wavelength pyrometry or reflectivity-compensated measurement to correct for emissivity effects. For laser anneal, the absorbed power depends on local film stack reflectivity, requiring pattern-density-aware scan recipes.
Dopant Activation and Deactivation: High peak temperatures drive substitutional incorporation of dopants into the silicon lattice, reducing sheet resistance. However, above certain concentrations (solid solubility limits), dopant clustering and precipitation occur during cooldown, leading to deactivation. Boron deactivation above approximately 2E20 cm-3 active concentration is a key concern for PMOS. Ultra-fast cooldown rates in millisecond anneal suppress deactivation by freezing the metastable high-activation state. Sequential anneal strategies combining a low-temperature SPER step with a high-temperature millisecond anneal optimize both crystal quality and activation.
Process Integration Considerations: Multiple anneal steps may be required throughout the CMOS flow: well anneals, source/drain extension activation, deep source/drain activation, and silicide formation anneals. The cumulative thermal budget from all steps must be tracked and managed. For gate-last HKMG flows, the replacement metal gate is inserted after all high-temperature source/drain anneals to protect the gate stack from thermal degradation. At advanced nodes, the total diffusion budget allows less than 1 nm of junction movement, necessitating millisecond anneal as the primary activation technique.
RTP spike and millisecond anneal technologies form the backbone of thermal processing in advanced CMOS, enabling the paradox of high-temperature activation with minimal atomic diffusion that defines competitive transistor performance.