Ruthenium and Alternative Metal Interconnects are the transition metals being evaluated as replacements for copper in the narrowest (M0, M1, M2) interconnect layers at sub-7nm nodes — where copper's effective resistivity increases dramatically at narrow widths due to surface and grain boundary scattering, while alternative metals like ruthenium (Ru), cobalt (Co), and molybdenum (Mo) may offer lower resistivity at narrow dimensions despite higher bulk resistivity, due to their longer electron mean free path and different scattering mechanisms.

The Copper Scaling Problem

• Bulk Cu resistivity: 1.7 µΩ·cm (excellent).
• At narrow width (10nm line): Electron mean free path (~40 nm) >> wire width → severe surface scattering.
• Cu effective resistivity at 10nm: 5–10 µΩ·cm (3–6× worse than bulk).
• Also: Cu needs Ta/TaN barrier (3–5 nm) + Cu seed → barrier+seed consumes ~40% of 10nm via volume → high resistance.
• Conclusion: At narrow widths, barrier overhead + scattering make Cu unattractive.

Ruthenium (Ru)

• Bulk resistivity: 7.1 µΩ·cm (4× worse than Cu).
• Advantage: Short electron mean free path (~6 nm) → less scattering at narrow widths.
• No barrier needed: Ru adheres directly to low-k dielectric without separate barrier → no volume lost.
• At 7nm width: Ru effective resistivity ≈ Cu effective resistivity (barrier-inclusive) → competitive.
• Ru ALD: Excellent step coverage → fills 5nm vias conformally.
• TSMC N5, N3: Ru used for M0 power rail and M1 local interconnect.

Cobalt (Co)

• Bulk resistivity: 6.2 µΩ·cm.
• Introduced at 14nm node (Intel, TSMC N7) for M0 and M1 local interconnect.
• Advantage: Better gap fill than W for narrow vias → lower via resistance.
• Selective CVD Co: Deposits preferentially on metal vs dielectric → self-aligned via capping.
• Replaced by Ru at N5/N3 for finest layers due to higher Ru mobility and better ALD process.

Molybdenum (Mo)

• Bulk resistivity: 5.2 µΩ·cm.
• Grain boundary scattering: Very short mean free path (~7 nm) → less degradation at narrow widths.
• Intel: Evaluating Mo for gate contact and M0 local interconnect at 18A/14A nodes.
• BEOL Mo: Low resistivity at 5–10nm widths → potentially best narrow-wire metal.
• Integration: CVD or ALD → good conformality.

Resistivity vs Width Comparison

Integration Considerations

• Ru CMP: Different slurry than Cu → KIO₄-based oxidizer → selectively removes Ru without dielectric damage.
• Ru reliability: EM (electromigration) resistance of Ru → preliminary data shows Ru EM lifetime similar to Co → still developing.
• Deposition: Ru ALD (RuO₄ precursor) → good step coverage in narrow vias; CVD alternative.
• Contact resistance: Ru-to-Si₃N₄ (no barrier) → contact resistance depends on interface preparation.

Strategy at Leading Nodes

• N3/N2 strategy: Cu for upper metals (M2 and above) where wider → Ru/Co for M0/M1 (narrow, local).
• "Metal-of-merit" by pitch: Each metal optimal at different width range → multi-metal interconnect in one chip.

Ruthenium and alternative metal interconnects are the BEOL response to copper's resistivity crisis at sub-10nm wire widths — as Moore's Law demands ever-narrower metal lines where copper's electron mean free path causes resistivity to triple or quadruple from bulk, the semiconductor industry is deliberately accepting higher bulk resistivity metals in exchange for eliminating thick barriers and exploiting short mean free paths that scale more favorably with wire width, marking the end of copper's 25-year monopoly on BEOL interconnect and beginning an era of metal-selection engineering where different metals serve different wire dimensions within the same chip's interconnect stack.