Home Knowledge Base SAR ADC (Successive Approximation Register Analog-to-Digital Converter)

SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is the most widely used ADC architecture that converts analog voltages to digital codes through a binary search algorithm — offering the best combination of moderate speed (1-100 MSPS), medium-to-high resolution (8-18 bits), low power consumption, and compact area that makes it the default choice for SoC-embedded data conversion.

How SAR ADC Works

1. Sample: Track-and-hold circuit captures the input voltage (Vin). 2. Compare MSB: Internal DAC set to Vref/2. Comparator checks: Is Vin > Vref/2?

3. Compare MSB-1: DAC adds/subtracts Vref/4. Compare again. 4. Repeat: N comparisons for N-bit resolution. 5. Output: N-bit digital code after N clock cycles.

Key Components

ComponentFunctionCritical Parameter
Capacitor DACGenerates comparison voltagesMatching (< 0.1% for 10-bit)
ComparatorCompares Vin vs DAC outputOffset, noise, speed
SAR LogicBinary search controllerSwitching sequence
Sample/HoldCaptures input voltageBandwidth, settling

Capacitive DAC (CDAC)

SAR ADC Advantages

SAR ADC vs. Other Architectures

ArchitectureSpeedResolutionPowerArea
SAR1-100 MSPS8-18 bitVery LowSmall
Pipeline100 MSPS-1 GSPS8-14 bitMediumLarge
Flash1-10 GSPS4-8 bitHighVery Large
Sigma-Delta< 10 MSPS16-24 bitLowMedium

Advanced SAR Techniques

SAR ADC is the workhorse data converter of the semiconductor industry — its elegant binary search algorithm delivers the optimal power-resolution-speed tradeoff that has made it the most prevalent ADC architecture in modern SoCs, from IoT sensors to 5G transceivers.

sar adc designsuccessive approximation adcsar adc architecturesar adc capacitorcomparator adc

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