Interfacial coalescence dynamics govern seam formation during thin-film gap fill in semiconductor manufacturing, where opposing chemical vapor deposition or atomic layer deposition fronts merge along feature centerlines. In nanoscale trenches and high aspect ratio contact vias, a seam represents a planar interface defect characterized by crystallographic grain misorientation, localized density deficits, and impurity entrapment. Eliminating seam defects across sub-2 nm logic nodes, FinFET gate-all-around architectures, and 3D NAND memory stacks requires rigorous co-optimization of film deposition conformality, trench sidewall taper angles, and post-metallization thermal recrystallization anneals.

Symmetrical sidewall deposition inevitably creates a centerline seam interface when opposing growth fronts coalesce. During isotropic chemical vapor deposition (CVD) or atomic layer deposition (ALD) performed on equipment from Applied Materials and Lam Research, thin-film material nucleates uniformly along all exposed trench surfaces. As the film thickness increases on opposing parallel sidewalls, the two advancing growth fronts approach the geometric centerline of the feature. Upon impingement, the atomic lattice orientations of the meeting polycrystalline or amorphous grains rarely align perfectly, resulting in a planar grain boundary discontinuity known as a centerline seam. In nanoscale interconnects with feature widths below 30 nm, this planar seam disrupts the continuous crystal lattice, creating localized mechanical stress concentration sites.

Impurity segregation along coalescing deposition fronts weakens the mechanical and chemical integrity of the seam. Process gases, precursor ligands, and residual reaction by-products (such as fluorine from $WF_6$, chlorine from $TiCl_4$, or organic carbon from organometallic precursors) tend to outgas and accumulate ahead of the advancing growth front. When opposing deposition fronts merge, these volatile impurities become trapped along the central interface. This chemical contamination lowers the local interfacial energy $\gamma_{seam}$, promoting micro-fracturing and rendering the seam highly susceptible to chemical attack during subsequent processing steps. Secondary ion mass spectrometry (SIMS) profiles confirm fluorine concentrations exceeding $1.0 \times 10^{19}\,\text{atoms/cm}^3$ localized along un-healed seam interfaces.

Chemical mechanical polishing decorates subsurface seams by exposing open crevice channels to abrasive slurries. During damascene metallization of tungsten plugs or copper interconnect lines, chemical mechanical polishing (CMP) removes overburden metal down to the surrounding dielectric stop layer. Mechanical abrasion by the CMP pad erodes the thin metal cap overlying the centerline seam. Once exposed, the acidic or basic CMP slurry enters the seam through capillary action ($h_{cap} = \frac{2 \gamma \cos\theta}{\rho g r}$), chemically etching and widening the interface into an open crevice. This phenomenon, known as seam decoration, causes severe slurry entrapment, post-polishing corrosion, outgassing, and catastrophic inter-line leakage.

Positive trench sidewall taper angles transform sharp centerline seams into self-closing V-shaped profiles. Etching trenches with a slight positive sidewall taper angle (typically between 87° and 89°) fundamentally alters the geometry of front coalescence. In a tapered feature, the trench width narrows progressively from top to bottom. During conformal deposition, opposing fronts coalesce first at the narrow trench base and move systematically upward. This bottom-up progressive closure prevents deep parallel seam trapping, forming a shallow, self-closing V-shaped seam near the top surface that is completely removed during standard CMP overburden planarization.

Superconformal electroplating eliminates centerline seams through differential additive adsorption. In dual damascene copper metallization, electroplating bath additives modulate the local deposition rate. Suppressor molecules (such as high-molecular-weight polyethylene glycol) adsorb rapidly on top surfaces and upper sidewalls, retarding copper deposition. Conversely, accelerator additives (such as disodium disulfide sulfonate, SPS) accumulate at the trench bottom due to surface area reduction during fill. This localized accelerator enrichment drives a bottom-up deposition rate 10 to 50 times faster than sidewall growth ($V_{bottom} \gg V_{sidewall}$), filling features seamlessly without forming a vertical centerline seam.

High-temperature hydrogen annealing drives grain boundary migration that dissolves planar seam defects. Following metal deposition, wafers undergo high-pressure thermal annealing at temperatures ranging from 400 °C to 450 °C under pure hydrogen ($H_2$) or forming gas atmospheres ($N_2/H_2$). The thermal energy activates atomic self-diffusion ($D_s = D_0 \exp(-E_a / k_B T)$) along grain boundaries, triggering recrystallization. As metal grains grow across the original impingement interface, the high-energy planar seam boundary dissolves, converting the bi-crystalline interface into a seamless, low-resistance monolithic metal structure.

Ruthenium and cobalt direct fill chemistries eliminate seam formation in sub-2 nm interconnect structures. As interconnect pitch shrinks below 20 nm, conventional copper damascene processes fail due to the excessive volume consumed by TaN/Ta barrier layers ($>2\,\text{nm}$). Cobalt ($Co$) and Ruthenium ($Ru$) can be deposited without thick barrier layers, exhibiting high atomic surface mobility during short-ratio CVD or thermal ALD. Under optimized reflow conditions at 350 °C, Co and Ru atoms migrate into feature corners before film fronts coalesce, producing a seamless, bottom-up fill front with zero centerline seam defects.

Knudsen transport depletion exacerbates seam width variance along deep vertical memory channels. In 3D NAND flash vertical memory holes with aspect ratios exceeding 80:1, precursor transport operates deep within the Knudsen diffusion regime ($Kn = \frac{\lambda}{d} \gg 1$). Wall-collision drag reduces precursor concentration toward the channel bottom, causing deposition rates to decrease continuously with depth. This depth-dependent growth rate variation creates a non-uniform seam profile that widens near the channel base, creating structural weak points susceptible to memory cell retention degradation and high-voltage breakdown.

Chemical wet etching decoration assays quantify seam severity during process development. To evaluate seam quality prior to full line integration, fab engineers execute chemical decoration tests. Cleaved or FIB-sectioned wafer samples are immersed in diluted hydrofluoric acid ($HF$) or hydrogen peroxide ($H_2O_2$) solutions for 5 to 10 seconds. The etchant selectively attacks the contaminated, low-density seam interface at a rate 20 to 100 times faster than bulk metal or dielectric. Scanning electron microscopy (SEM) measurement of the decorated crevice width provides a quantitative metric of seam contamination.

Parasitic resistance increases dramatically when centerline seams disrupt electron mean free path. In ultra-narrow tungsten or copper lines ($w < 15\,\text{nm}$), electrical conduction is heavily constrained by surface and grain boundary scattering. A continuous centerline seam acts as a planar electron scattering barrier aligned directly along the primary current conduction path. Conduction electrons undergo specular and diffuse reflection at the seam interface, increasing effective electrical resistivity $\rho$ by 30 to 80 percent above bulk values according to the Fuchs-Sondheimer and Mayadas-Shatzkes conductivity models.

Atomic layer deposition pulse-purge timing optimization minimizes seam impurity trapping. In thermal ALD of tungsten ($W$) using $WF_6$ and $SiH_4$ or $B_2H_6$ reductants, incomplete purging of reaction by-products traps fluorine ($F$) and silicon ($Si$) atoms at the seam impingement front. By extending the purge duration from 500 ms to 2.0 s and raising reaction temperatures to 300 °C, unreacted precursor species are completely evacuated from the trench volume before front coalescence occurs, reducing seam fluorine contamination below $1.0 \times 10^{18}\,\text{atoms/cm}^3$.

Stress concentration along un-healed seams causes dielectric delamination under thermal cycling. Because centerline seams possess lower mechanical fracture toughness ($K_{IC} < 0.5\,\text{MPa}\cdot\text{m}^{1/2}$) than bulk metal or dielectric films, thermo-mechanical stresses concentrate along the seam line during thermal cycling between -40 °C and 125 °C. When hydrostatic tensile stress exceeds the degraded interfacial strength of the seam, micro-cracks propagate vertically through the metal line, eventually peeling adjacent low-k organosilicate glass (OSG) dielectric layers.

Selective area deposition prevents seam formation by eliminating sidewall growth components. Selective Area Chemical Vapor Deposition (SACVD) and Selective ALD utilize self-assembled monolayers (SAMs) or chemical inhibitors to block deposition on feature sidewalls while permitting bottom-up growth on underlying conductive seeds. Because material grows exclusively from the bottom surface upward ($V_{bottom} > 0, V_{sidewall} = 0$), opposing sidewall fronts never meet, completely eliminating the physical mechanism of seam formation.

In situ plasma treatment during gap fill enhances interfacial bonding across meeting growth fronts. Incorporating periodic RF plasma treatments ($NH_3$ or $H_2/Ar$ plasma pulses) between deposition cycles cleans species from advancing film surfaces. Plasma-generated radicals bombard the sidewall fronts, removing organic contaminants and reducing native oxides immediately prior to coalescence. This in situ surface activation promotes direct metallic or covalent bond formation across the impingement interface, strengthening the seam against post-CMP slurry attack.

Advanced 3D TCAD simulations predict seam location and morphology based on level-set surface kinetics. Modern Technology Computer-Aided Design (TCAD) simulation suites (including Synopsys Sentaurus Process and Silvaco Victory Process) utilize level-set algorithms to track advancing deposition boundaries. By incorporating Knudsen precursor transport, surface sticking coefficients, and grain boundary growth vectors, 3D TCAD models accurately forecast the exact spatial coordinates of seam formation, allowing process engineers to optimize trench geometry and deposition parameters prior to mask tape-out.

Electromigration lifetime degrades when vacancies accumulate along high-diffusivity seam paths. Under high direct current stress ($J > 1.5\,\text{MA/cm}^2$), the un-coalesced grain boundaries along a centerline seam act as high-speed diffusion pipelines for metal vacancies. The vacancy diffusion coefficient along an un-healed seam $D_{seam}$ is up to three orders of magnitude higher than bulk lattice diffusion ($D_{bulk}$). Vacancies rapidly migrate along the seam toward cathode terminals, accelerating void nucleation and reducing Mean Time to Failure (MTTF) by more than 60 percent.

Spectroscopic ellipsometry and optical scatterometry detect seam-induced surface topography variations. In line-and-space patterns, post-CMP seam decoration creates subtle surface topography dips on the order of 1 to 3 nm. High-throughput broadband plasma scatterometry tools analyze polarized light reflection spectra from these decorated patterns. Machine learning algorithms correlate subtle phase shifts in the reflected spectra with seam crevice depth, enabling non-destructive inline monitoring of seam decoration severity across entire 300 mm production wafers.

Reflow-assisted physical vapor deposition seals surface seam openings prior to CMP. Ionized PVD (iPVD) deposition of aluminum or copper seed layers can be integrated with in situ thermal reflow. By maintaining the electrostatic chuck at 350 °C during sputter deposition, energetic metal ions arriving at the surface undergo rapid surface self-diffusion ($D_s = D_0 \exp(-E_a / k_B T)$). The mobile metal atoms flow into surface seam crevices, filling the top 20 nm of the seam opening and sealing the feature against CMP slurry penetration.

Foundry PDK design rules restrict maximum feature widths to prevent un-fillable seam voids. Semiconductor Process Design Kits (PDKs) from leading foundries (including TSMC, Intel, Samsung, and GlobalFoundries) enforce strict maximum width constraints ($W_{max}$) on contact and via structures. If a contact feature exceeds $W_{max}$ (typically 100 nm for tungsten contacts), conformal deposition fails to bridge the center, leaving a wide, hollow seam opening. PDK DRC decks automatically flag non-compliant wide slots, forcing designers to split large contacts into arrays of sub-resolution contact vias.

Supercritical fluid cleaning removes trapped CMP slurry residues from exposed seam channels. When post-CMP rinses fail to clean aqueous slurry chemicals trapped deep inside open seam crevices, wafers are processed in supercritical carbon dioxide ($sCO_2$) cleaning systems. Operating above the critical point ($31.1\,°C, 7.38\,\text{MPa}$), $sCO_2$ exhibits zero surface tension and gas-like diffusivity. The supercritical fluid penetrates deep into sub-nm seam crevices, dissolving and extracting residual slurry oxidizers and organic surfactants without causing pattern collapse.

Void transition kinetics govern the transformation of centerline seams into isolated keyholes. When deposition step coverage drops below 70 percent, top overhang growth accelerates faster than sidewall coalescence. The top mouth pinches off before the vertical seam completes its bottom-up closure, trapping an isolated gas pocket along the lower seam line. This hybrid seam-keyhole defect combines the high capillary pressure of an internal void with the mechanical weakness of a planar interface, presenting severe reliability risks during thermal cycling.

Grain growth inhibitors in tungsten deposition chemistries alter seam coalescence profiles. Introducing trace amounts of grain growth inhibitors (such as nitrogen or carbon) during chemical vapor deposition of tungsten alters the microstructural evolution of advancing film fronts. Inhibitors refine the film grain size down to sub-5 nm dimensions, creating an ultra-fine nanocrystalline structure. Upon coalescence, the high density of microscopic grain boundaries distributes interfacial mismatch evenly, preventing the formation of a single continuous planar seam line.

Backside power delivery networks require seam-free vertical TSV refill for high-current conduction. In backside power delivery network (BSPDN) architectures and 3D silicon interposers, Through-Silicon Vias (TSVs) reach depths of 50 µm with aspect ratios of 10:1. Passing high supply currents ($I > 2.0\,\text{A}$) through TSVs containing centerline seams induces localized resistive heating ($I^2 R$) and electromigration failure. Fab flows mandate multi-step electroplating with periodic reverse pulse currents to guarantee 100 percent seam-free TSV metallization.

Aberration-corrected TEM enables atomic-scale visualization of seam grain misorientation angles. Characterizing atomic bonding across coalesced seam interfaces requires Transmission Electron Microscopy (TEM) operating at sub-angstrom resolution ($<0.08\,\text{nm}$). High-Angle Annular Dark-Field (HAADF) STEM imaging visualizes individual atomic columns across the seam line, allowing materials scientists to measure grain tilt angles and quantify vacancy concentrations along the impingement interface to validate atomistic deposition models.

Cryogenic post-etch cleaning suppresses seam decoration by preventing chemical over-etching. Following CMP and dielectric cap etching, wafers undergo post-clearing rinses. Executing chemical cleaning steps at cryogenic temperatures (-20 °C to 5 °C) reduces chemical reaction rates while maintaining solvent solubility. The lower thermal energy prevents aggressive etchants from penetrating into micro-seams, suppressing seam decoration width by over 75 percent compared to room-temperature cleaning.

Electronic Design Automation tools run timing sign-off checks on seam-induced delay variations. EDA timing engines (such as Synopsys PrimeTime and Cadence Tempus) import parasitic extraction netlists containing seam-induced resistance adders. If a critical signal path traverses narrow tungsten contacts containing un-healed seams, the tool calculates the localized RC delay penalty $\Delta \tau = R_{seam} C_{net}$. If setup slack falls below zero ($S_{setup} < 0\,\text{ps}$), the tool triggers automated buffer insertion or wire widening to restore timing sign-off compliance.

High-pressure argon annealing seals micro-seam openings through isotropic surface compaction. In addition to hydrogen annealing, processing wafers in high-pressure argon ($Ar$) chambers at 200 atm and 400 °C applies isotropic hydrostatic compression to deposited metal films. The immense gas pressure forces opposing seam walls into atomic contact, accelerating solid-state diffusion and cold-welding micro-seam crevices closed without introducing chemical reactive species into the metal lattice.

In situ spectroscopic ellipsometry monitors real-time seam closure dynamics during ALD reflow. Modern atomic layer deposition platforms incorporate multi-wavelength spectroscopic ellipsometry ports to monitor thin film optical properties in real-time. As sidewall deposition fronts coalesce, the effective refractive index $n$ and extinction coefficient $k$ of the film stack exhibit characteristic transition shifts. Process controllers utilize these optical signatures to detect the exact millisecond of front coalescence, dynamically triggering thermal reflow cycles to heal seam interfaces before subsequent deposition steps proceed.

Grain orientation mapping via electron backscatter diffraction quantifies seam recrystallization efficiency. To verify that thermal annealing successfully dissolves centerline seam interfaces, failure analysis engineers employ High-Resolution Electron Backscatter Diffraction (HR-EBSD). By mapping crystal lattice orientation with 10 nm spatial resolution, EBSD scans reveal whether original impingement boundaries maintain high-angle grain misorientation ($>15^\circ$) or have fully migrated into low-energy twin boundaries ($\Sigma 3$) or seamless monolithic grains. Achieving zero high-angle seam boundaries guarantees 100 percent electrical and mechanical reliability sign-off.

Multi-layer interconnect stack thermal expansion mismatches induce interfacial shear along seams. In modern multi-level metal stacks with up to 15 wiring layers, each metal line is encased by low-k dielectric, barrier metal, and etch-stop caps. Because the coefficient of thermal expansion (CTE) of copper ($16.5 \times 10^{-6}/\text{K}$) differs significantly from silicon nitride ($3.3 \times 10^{-6}/\text{K}$) and organosilicate glass ($2.0 \times 10^{-6}/\text{K}$), temperature excursions during backend-of-line (BEOL) packaging induce severe shear stress along un-healed seam lines. Shear stress values exceeding 150 MPa trigger interfacial sliding along the seam, leading to intermittent open-circuit faults.

Cryogenic focused ion beam sample preparation preserves delicate seam structures for metrology. Conventional room-temperature Focused Ion Beam (FIB) milling introduces thermal artifacts and gallium ($Ga^+$) ion implantation that can artificially weld or melt micro-seam openings. Cool-stage Cryo-FIB milling at -160 °C stabilizes fragile low-density seam interfaces, preventing ion-beam-induced grain boundary migration. This ultra-clean cross-sectioning protocol enables pristine High-Resolution SEM visualization of seam crevice widths as small as 0.5 nm.

Secondary ion mass spectrometry depth profiling tracks ligand outgassing along seam channels. Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS) provides 3D chemical mapping of impurity distributions with sub-nanometer depth resolution. By sputtering through metallized contact vias, SIMS depth profiles trace the exact molecular origin of seam contamination—distinguishing between precursor ligands ($F, Cl, C$), atmospheric moisture ($H_2O, OH$), and CMP slurry complexes. Fabs use these 3D SIMS maps to optimize precursor dosing ratios and chamber bake-out cycles.

Machine learning classifiers predict post-CMP seam decoration yields from inline scatterometry. Modern 300 mm fab lines collect gigabytes of inline scatterometry data across every wafer lot. Deep convolutional neural networks trained on cross-sectional TEM ground truth datasets analyze polarized optical reflection spectra immediately post-fill. The machine learning model flags subtle spectral anomalies indicative of sub-surface seam crevice widening, predicting post-CMP electrical yield with 99 percent accuracy and automatically redirecting defective wafers for high-pressure $H_2$ recovery annealing.

Ultra-low-k dielectric pore sealing prevents precursor condensation during seam gap fill. In sub-2 nm BEOL interconnects, porous organosilicate glass (OSG, $\kappa = 2.1$) dielectrics incorporate micro-porosity to minimize capacitance. When ALD or CVD metal deposition begins, precursors penetrate into exposed sidewall pores, creating non-uniform nucleation sites that accelerate local overhang formation. Fabs apply remote plasma pore sealing ($NH_3/He$ plasma) prior to gap fill, forming a 0.5 nm dense barrier layer that forces uniform 1D growth fronts and eliminates pore-induced seam widening.

Atomistic reactive molecular dynamics simulations model ligand detachment at seam interfaces. Complementing continuum TCAD, atomistic Reactive Force Field (ReaxFF) molecular dynamics simulations track individual precursor ligand detachment events during $WF_6$ and $H_2$ reaction cycles. ReaxFF models reveal that fluorine atoms remain bound to step edges on (110) tungsten crystallographic planes, creating localized steric hindrance that delays front coalescence. Process engineers use atomistic kinetics to design pulsed hydrogen plasma steps that selectively strip trapped fluorine before front impingement occurs.

Synchrotron radiation X-ray fluorescence microscopy maps trace metal impurities along seam crevices. Synchrotron-based Nanoprobe X-ray Fluorescence (nXRF) microscopy provides sub-10 nm elemental imaging capabilities. By raster-scanning a micro-focused X-ray beam across metallized interconnect arrays, nXRF maps trace metal contamination ($Fe, Ni, Cr$) and halogen residues ($F, Cl$) trapped along centerline seams with high sensitivity ($< 10^{15}\,\text{atoms/cm}^2$). Fabs use these synchrotron chemical maps to validate zero-contamination seam closure protocols.

Integrated fab execution protocols combine layout DRC, chemical optimization, and thermal annealing for 100 percent seam elimination. Eliminating seam defects across advanced semiconductor technologies requires a holistic engineering strategy. Process engineers must balance trench taper angles, ALD pulse-purge timings, superconformal plating bath additives, and post-metallization thermal budgets with EDA design rule decks. Establishing full compliance across physical manufacturing, TCAD simulation, and electrical sign-off guarantees seam-free interconnects capable of supporting 25-year device operational lifetimes.

Appendix: Advanced Physical Kinetics & Fab Implementation Details

Comparative Matrix of Seam Formation Characteristics & Fab Mitigation Strategies

graph TD
    A["Inline Defect & Metrology Scan<br/>(HR-TEM / EBSD / Optical Scatterometry)"] --> B{"Centerline Seam Defect Detected?"}
    B -- No --> C["Proceed to CMP & Interconnect Sign-Off<br/>(PASS)"]
    B -- Yes --> D{"Evaluate Seam Severity & Location"}

    D -- "Open Crevice (CMP Slurry Ingress)" --> E["Analyze Post-CMP Surface Topography"]
    E --> E1["Apply High-Pressure H2 Anneal<br/>(T = 400 °C, P = 25 atm)"]
    E1 --> E2["Deploy Supercritical CO2 Cleaning"]

    D -- "Impurity Contamination (F/Cl/C)" --> F["Assess ALD Purge Kinetics"]
    F --> F1["Extend ALD Purge Duration to > 2.0 s"]
    F1 --> F2["Increase Deposition Temperature T"]

    D -- "Parallel Front Impingement" --> G["Inspect Trench Sidewall Profile"]
    G --> G1{"Is Taper Angle < 87°?"}
    G1 -- Yes --> G2["Adjust Etch Process to Provide 3° Taper"]
    G1 -- No --> G3["Switch to Superconformal Bottom-Up Fill"]

    D -- "High Line Resistance (Electron Scattering)" --> H["Check Interconnect Width w"]
    H --> H1["Deploy Barrierless Co/Ru Direct Fill"]

    E2 --> I["Re-Inspect via FIB-SEM & HR-TEM"]
    F2 --> I
    G2 --> I
    G3 --> I
    H1 --> I
    I --> J{"100% Seam Elimination Confirmed?"}
    J -- Yes --> C
    J -- No --> K["Trigger PDK DRC Rule Revision<br/>(Restrict Max Feature Width W_max)"]

Interfacial free energy minimization dictates the thermodynamic stability of a centerline seam during thermal processing. The net change in free energy $\Delta G_{seam}$ associated with converting two free surfaces of area $A_s$ into a grain boundary interface of area $A_{gb}$ is expressed as:

Because the specific surface free energy of a deposited metal $\gamma_s$ (typically $1.5$ to $2.2\,\text{J/m}^2$) significantly exceeds its grain boundary energy $\gamma_{gb}$ (typically $0.4$ to $0.8\,\text{J/m}^2$), front coalescence is thermodynamically favorable ($\Delta G_{seam} < 0$). However, if volatile impurities adsorb on the free surfaces prior to impingement, $\gamma_s$ drops precipitously, decreasing the driving force for seam healing and trapping a persistent high-energy interface.

Fuchs-Sondheimer Mayadas-Shatzkes resistivity modeling

The electrical resistance adder introduced by a centerline seam in nanoscale conductors is modeled by combining the Fuchs-Sondheimer surface scattering theory with the Mayadas-Shatzkes grain boundary scattering model. The ratio of effective seam-affected resistivity $\rho_{eff}$ to bulk resistivity $\rho_0$ is given by:

where the dimensionless grain boundary scattering parameter $\alpha$ is defined as:

Here, $\lambda_0$ is the intrinsic electron mean free path ($39\,\text{nm}$ for copper, $15\,\text{nm}$ for tungsten), $d_{grain}$ is the average grain size, and $R_{seam}$ is the electron reflection coefficient at the seam boundary ($0 \le R_{seam} \le 1$). When an un-healed seam exhibits $R_{seam} \approx 0.7$, electrical resistivity increases by over 50 percent in 15 nm wide interconnect lines.

Preston CMP seam erosion dynamics

During chemical mechanical polishing of metal damascene structures containing exposed centerline seams, mechanical polishing pad abrasion and chemical dissolution act synergistically. The Preston equation models the localized material removal rate $R_p$:

where $K_P$ is the Preston coefficient, $P$ is down-force pressure, and $V$ is relative platen velocity. At an exposed seam crevice, mechanical stress concentrations elevate local pressure $P_{local} = P_{macro} \left(1 + \frac{a}{r}\right)$, accelerating the localized removal rate $R_{p,seam}$ relative to the bulk metal removal rate. This differential polishing rate widens the seam opening into a V-shaped slurry crevice.

Standardized closing lens statement

Read seam through a coupled coalescence-interface-thermodynamic lens rather than a single-line-defect lens.