Selective Epitaxial Growth (SEG) for Raised Source/Drain is the CMOS process technique that deposits crystalline silicon or silicon-germanium only on exposed silicon surfaces while leaving dielectric regions (oxide, nitride) bare — enabling raised source/drain (RSD) structures that increase the volume of doped semiconductor at the transistor contact, reducing parasitic series resistance by 30-50% and providing strain engineering capability that boosts channel mobility for both NMOS and PMOS devices at advanced nodes.
Why Selective Epitaxy
- Contact resistance: Major limiter at sub-14nm nodes → more contact area = less resistance.
- Non-selective deposition: Grows everywhere (Si + dielectric) → requires complex etch-back.
- Selective growth: Deposits only on Si → self-aligned, no additional patterning needed.
- SiGe for PMOS: Compressive strain on channel → 40-60% hole mobility improvement.
- SiC/Si:P for NMOS: Tensile strain → 10-20% electron mobility improvement.
SEG Process Chemistry
| Precursor | Material | Temperature | Selectivity Agent |
|---|---|---|---|
| SiH₂Cl₂ (DCS) + GeH₄ | SiGe | 550-650°C | HCl gas (etches nuclei on dielectric) |
| SiH₄ + GeH₄ | SiGe | 450-550°C | Cl₂ or HCl co-flow |
| SiH₂Cl₂ + PH₃ | Si:P | 600-700°C | HCl intrinsic selectivity |
| Si₂H₆ + B₂H₆ + GeH₄ | B:SiGe | 450-550°C | HCl co-flow |
Selectivity Mechanism
- Si surface: Precursor chemisorbs on dangling bonds → nucleation → epitaxial growth.
- SiO₂/SiN surface: No dangling bonds → precursor does not chemisorb → no nucleation.
- HCl role: Any stray nuclei on dielectric are etched by HCl before they grow → maintains selectivity.
- Selectivity window: Temperature/pressure/HCl-flow range where growth on Si >> growth on dielectric.
- Loss of selectivity: Too high temperature or too low HCl → polycrystalline deposits on dielectric.
RSD Structure in FinFET/GAA
- FinFET PMOS: Recess fin → SEG SiGe fills recess + grows above fin → diamond-shaped raised S/D.
- Merge vs. unmerge: Adjacent fins can merge epitaxy (lower resistance) or stay separate (less defects).
- GAA/nanosheet: S/D epitaxy wraps around multiple nanosheets → complex 3D growth.
- In-situ doping: B (for PMOS) or P (for NMOS) incorporated during growth → eliminates implant step.
Key Process Challenges
| Challenge | Cause | Mitigation |
|---|---|---|
| Facet formation | Crystal orientation dependent growth rates | Optimize temperature/pressure |
| Loading effect | Pattern density affects local growth rate | Recipe tuning per layout |
| Ge composition uniformity | Gas depletion across wafer | Multi-zone gas injection |
| Defect at epi/substrate interface | Surface contamination | Pre-epi HF clean + H₂ bake |
| Selectivity loss | Nucleation on nitride spacer | Higher HCl flow, lower temperature |
Pre-Epitaxy Clean
- Critical: Any native oxide on Si surface → blocks epitaxial growth → defective interface.
- Sequence: Dilute HF dip → DI rinse → H₂ bake at 800°C → in-situ HCl etch → growth.
- SiCoNi/COR: Dry clean alternative for advanced nodes (no wet transfer exposure).
- Time budget: < 2 hours from clean to load → minimizes native oxide regrowth.
Selective epitaxial growth is the enabling process technology for modern transistor source/drain engineering — by providing self-aligned, in-situ doped, strain-inducing semiconductor regions exactly where needed, SEG eliminates the performance-limiting parasitic resistance while simultaneously delivering the channel strain that is responsible for a significant fraction of the performance gain at each new technology node.
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