Selective Etching is the process of removing one material preferentially while leaving adjacent materials intact — with selectivity quantified as the ratio of etch rates between target and non-target materials, critical for every patterning step in CMOS.

What Is Selectivity?

• Selectivity S = $\frac{ER_{target}}{ER_{non-target}}$
• Example: HF etches SiO2 at 100 nm/min but Si at < 0.1 nm/min → S > 1000:1.
• Practical requirement: S > 10:1 for process control; S > 100:1 for aggressive processes.

Key Selective Etch Applications in CMOS

STI Nitride Removal:

• H3PO4 (165°C): Si3N4:SiO2 selectivity ~ 40:1.
• Removes polish-stop nitride without significant oxide loss.

Gate Oxide Removal (Pre-Gate):

• Dilute HF or BOE: SiO2:Si selectivity > 100:1.
• Removes interfacial oxide to enable clean high-k deposition.

SiGe Channel Selective Etch (FinFET → GAAFET):

• HCl gas at 600–700°C: Etches SiGe but not Si.
• Or SC-1: H2O2 + NH4OH + H2O etch SiGe selectively.
• Selectivity Si:SiGe > 100:1 enables nanosheet channel release.

Si Etch with Selectivity to SiGe:

• TMAH: Si:SiGe selectivity ~20:1 for GAAFET nanosheet formation.

Replacement Gate Etch (Gate Last):

• APM (SC-1): Removes poly-Si gate with high selectivity to gate dielectric and spacers.
• Poly:SiO2 selectivity ~50:1; Poly:SiN (spacer) selectivity > 100:1.

Mechanisms of Selectivity

• Chemical: Different bond energies (Si-F is strong; SiO2-F is stronger).
• Passivation: Etch by-products passivate non-target surfaces (e.g., SiF4 passivates Si in Cl2 plasma).
• Thermodynamic: Gibbs free energy of reaction — spontaneous for target, non-spontaneous for non-target.

Improving Selectivity

• Reduce ion bombardment → chemistry-dominated → higher selectivity.
• Add passivation gases (CHF3, CH4) to protect non-target surfaces.
• Optimize temperature: Some selectivities are strongly temperature-dependent.

Selective etching is the engineering foundation of all CMOS process integration — without precise selectivity control, the self-aligned process flows that enable transistor scaling at single-digit nanometers would be impossible.