Selective Tungsten Deposition is the area-selective chemical vapor deposition process that nucleates and grows tungsten metal preferentially on metallic surfaces while suppressing growth on dielectric surfaces, enabling bottom-up void-free filling of high-aspect-ratio contacts and self-aligned metallization schemes that eliminate costly lithography and etch steps at advanced CMOS nodes.
Selectivity Fundamentals:
- Surface Energy Difference: tungsten CVD precursor (WF₆) readily chemisorbs on metallic surfaces (TiN, Co, W) through ligand exchange but has high nucleation barrier on SiO₂ and SiN due to lack of reducing surface species
- Nucleation Delay: on thermal SiO₂, WF₆ + SiH₄ chemistry exhibits 10-50 cycle nucleation delay during which no measurable W deposits—this incubation period defines the selectivity window
- Selectivity Ratio: defined as thickness on growth surface divided by thickness on non-growth surface—production targets require >100:1 selectivity for >10 nm selective growth
- Self-Limiting Passivation: surface inhibitor molecules (small-molecule inhibitors or SAMs) preferentially adsorb on dielectric surfaces, extending nucleation delay from 50 cycles to >200 cycles
Deposition Chemistry and Process:
- Precursor System: WF₆ with SiH₄, Si₂H₆, or B₂H₆ reducing agents at 250-350°C and 1-40 Torr—lower temperatures favor selectivity but reduce growth rate
- ALD-like Pulsing: alternating WF₆ and reducing agent pulses with N₂ purge between each provides better selectivity than continuous CVD by limiting gas-phase reactions
- Growth Rate: typical selective W growth rate of 0.5-2.0 nm/cycle on metal surfaces with <0.1 nm/cycle on dielectric—growth rate depends on substrate temperature and precursor partial pressure
- Fluorine Management: WF₆ decomposition releases fluorine that attacks underlying TiN barrier and can penetrate to Si substrate—B₂H₆ co-flow scavenges free fluorine, reducing F content in W film to <0.1 atomic %
Surface Inhibitor Technologies:
- Small-Molecule Inhibitors (SMIs): molecules such as dimethylamino trimethylsilane (DMATMS) or aniline selectively adsorb on —OH terminated dielectric surfaces through hydrogen bonding, blocking WF₆ chemisorption
- Self-Assembled Monolayers (SAMs): octadecyltrichlorosilane (ODTS) or similar long-chain silanes form dense hydrophobic layers on SiO₂—provides >1000:1 selectivity but requires thermal stability at deposition temperature
- Plasma Pre-Treatment: selective H₂ or NH₃ plasma treatment activates metal surfaces (removes native oxide) while passivating dielectric surfaces with nitrogen-containing species
- Inhibitor Refresh: selectivity degrades after 5-15 nm of growth due to inhibitor decomposition—periodic process interruption to refresh inhibitor layer extends selective growth window
Applications in Advanced MOL/BEOL:
- Contact Fill: selective W nucleation on Co or TiN liner at contact bottom enables bottom-up fill without centerline seams—eliminates voids in contacts with aspect ratios >10:1 at N3/N2 nodes
- Self-Aligned Capping: selective W growth on exposed copper lines forms protective cap without lithography—prevents copper electromigration and oxidation at <30 nm line widths
- Via Pre-Fill: selective W deposition at via bottom prior to Cu electroplating improves via resistance by 15-25% and eliminates barrier coverage concerns in high-AR vias
- Interconnect Scaling: barrier-less selective W for semi-damascene integration reduces total metal line resistance by eliminating 2-4 nm of resistive barrier material from each sidewall
Defectivity and Process Control:
- Selectivity Loss Detection: in-line reflectance spectroscopy or XRF mapping detects unwanted W nucleation on dielectric surfaces before it propagates into yield-killing defects
- Particle Control: WF₆ gas-phase reactions with SiH₄ can generate W particles in the chamber—controlled through precise precursor delivery timing and regular chamber plasma cleaning
- Uniformity: within-wafer thickness uniformity <3% achieved through showerhead design optimization and multi-zone temperature control
Selective tungsten deposition is emerging as a key enabling technology for sub-3 nm interconnect integration, where its ability to provide bottom-up metal fill and self-aligned metallization directly addresses the two most critical scaling challenges of void-free contact formation and overlay-free via patterning that constrain conventional blanket deposition and etch approaches.
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