Multi-Patterning Aware Layout (SADP/SAQP) is the design methodology where layout patterns at sub-wavelength pitches are decomposed into multiple mask exposures, because a single lithographic exposure cannot resolve features below ~38nm half-pitch with 193nm immersion lithography — requiring Self-Aligned Double Patterning (SADP) or Self-Aligned Quadruple Patterning (SAQP) that impose specific design rule constraints on the layout.

At 7nm and below, critical metal layers (M0-M3) have pitches of 28-36nm — well below the ~76nm resolution limit of single-exposure 193i lithography. Multi-patterning decomposes these tight-pitch patterns into multiple masks, each within the lithographic resolution limit, with process self-alignment ensuring accurate overlay.

Patterning Technologies:

SADP Process Flow: A mandrel layer is patterned at relaxed pitch (2x target). Spacers are conformally deposited on mandrel sidewalls. The mandrel is selectively removed, leaving free-standing spacers at the target pitch. Key constraint: spacer-defined features have uniform pitch — you cannot have arbitrary spacing between adjacent wires. This creates the fundamental SADP design rule: certain wire spacings are "legal" (multiples of the spacer pitch) and others are forbidden.

Design Rule Implications: Multi-patterning imposes coloring constraints — where each wire must be assigned to a specific mask (color), and wires on the same mask must satisfy the per-mask minimum spacing (which is relaxed relative to the final pitch). Color conflicts occur when the coloring algorithm cannot assign legal colors to all wires — requiring the router to adjust wire positions. Tip-to-tip rules (minimum end-to-end spacing between wires on the same mask) are typically much larger than side-to-side spacing, creating asymmetric routing constraints.

EDA Tool Support: Multi-patterning-aware routers (Innovus, ICC2) incorporate coloring as a real-time routing constraint — the tool simultaneously routes and colors wires, avoiding color conflicts by construction. Decomposition verification tools check that the final layout can be legally decomposed into the required number of masks. Overlay-aware timing analysis accounts for the additional variability from multi-mask alignment errors.

EUV Impact: EUV lithography (13.5nm wavelength) can single-expose patterns that would require SADP with 193i, simplifying the patterning and relaxing design rules. However, at the tightest pitches (3nm node and below), even EUV requires double patterning (EUV + SADP), and stochastic printing effects (shot noise due to few EUV photons per feature) introduce new variability concerns.

Multi-patterning aware layout is the bridge between transistor scaling ambitions and lithographic reality — it enables the semiconductor industry to continue producing denser chips at ever-smaller nodes, but at the cost of increased design complexity, manufacturing cost, and variability that design teams must actively manage.