Self-Aligned Via SAV Process — The self-aligned via (SAV) process eliminates the dependence on lithographic overlay accuracy for via-to-metal alignment by using the metal pattern itself as a guide for via formation, enabling tighter interconnect pitches and improved yield at advanced CMOS technology nodes.

Concept and Motivation — Traditional via patterning relies on lithographic alignment between via and metal layers:

• Overlay budget at sub-7nm nodes requires alignment accuracy below 2nm, which approaches the limits of current lithography tools
• Via-to-metal misalignment can cause partial via landing, increased resistance, and reliability failures due to reduced contact area
• Self-aligned approaches decouple via placement accuracy from overlay by using topographic or material-selective processes
• Pitch scaling below 28nm metal pitch makes conventional via alignment increasingly difficult and yield-limiting
• Design rule relaxation enabled by SAV allows more aggressive via placement without guard-banding for overlay errors

SAV Process Approaches — Multiple self-aligned via integration schemes have been developed:

• Selective etch-back of metal lines below the dielectric surface creates recesses that are filled with a different dielectric, forming a self-aligned etch stop pattern
• Selective metal cap deposition on copper or cobalt surfaces creates a hard mask that protects metal lines during via etch
• Dielectric-on-dielectric selectivity uses different dielectric materials for inter-line fill and via-level dielectric to achieve self-aligned etch stop behavior
• Tone inversion approaches create a complementary pattern of the metal lines in a different material to guide via etch landing
• Fully self-aligned via (FSAV) extends the concept to align vias to both the underlying and overlying metal patterns simultaneously

Process Integration Details — Implementing SAV requires careful material selection and process sequencing:

• Selective deposition of capping materials must achieve high selectivity between metal and dielectric surfaces to create the alignment features
• Etch selectivity between the via-level dielectric and the self-aligned etch stop material must exceed 10:1 to ensure reliable via landing
• Metal recess uniformity across the wafer and between different pattern densities is critical for consistent SAV performance
• CMP integration must preserve the self-aligned features while achieving the required planarity for subsequent lithography
• Thermal budget constraints limit the choice of materials and deposition processes to those compatible with existing BEOL structures

Benefits and Limitations — SAV provides significant advantages but introduces new process complexity:

• Overlay tolerance is relaxed by 50–70% compared to conventional via patterning, directly improving yield at tight pitches
• Via resistance uniformity improves because all vias land fully on the metal line regardless of lithographic overlay variation
• Electromigration reliability benefits from consistent via-to-metal contact area and elimination of partial landing configurations
• Process complexity increases due to additional deposition, etch, and CMP steps required to create the self-aligned features
• Material compatibility constraints may limit the choice of metals and dielectrics at certain technology nodes

Self-aligned via technology is a critical enabler of interconnect scaling at the most advanced nodes, transforming via alignment from a lithographic challenge into a materials and etch engineering problem with significantly wider process margins.