Semiconductor Cost Modeling and Fab Economics is the analytical framework for calculating the cost of manufacturing semiconductor devices — decomposing total cost into equipment depreciation, materials, labor, overhead, and yield loss to determine cost-per-die and cost-per-wafer-start, enabling foundries and IDMs to make process technology investment decisions, set pricing, benchmark efficiency, and optimize the trade-offs between die size, yield, and technology node selection.

Cost Per Die Formula

Cost per die = Wafer cost / (Dies per wafer × Yield)

Dies per wafer = (Wafer area - Edge area) / Die area
                = π × (R² - R×√(2×Die area)) / Die area

Yield (negative binomial) = (1 + D₀×A/α)^(-α)
  where:
    D₀ = defect density (defects/cm²)
    A  = die area (cm²)
    α  = clustering parameter (typically 0.5–3)

Wafer Cost Components

Cost Scaling with Node

• Wafer cost has increased dramatically at advanced nodes:
• 28nm wafer: ~$2,000–3,000
• 7nm wafer: ~$7,000–9,000
• 3nm wafer: ~$15,000–20,000
• 2nm wafer (projected): > $25,000
• Reason: More process steps, EUV passes, complex patterning → longer cycle time, more equipment.

Equipment Cost and Depreciation

• ASML EUV scanner (NXE:3600): ~$200M per unit → depreciated ~$28M/year (7 years).
• EUV requires 1 scanner per 45,000 wafer starts per month (WSPM) → significant cost per wafer.
• Total fab CapEx: Leading-edge fab: $15–25B → amortized over wafer starts.
• Cost of ownership (CoO): Annual cost to own/operate tool ÷ productive wafer output → $/wafer-pass.

Yield vs Die Area Trade-off

Example: 7nm node, D₀ = 0.1 defects/cm², wafer cost = $8,000

5mm × 5mm die (0.25 cm²): Y = (1 + 0.1×0.25/1)^(-1) = 0.976 → 97.6%
15mm × 15mm die (2.25 cm²): Y = (1 + 0.1×2.25/1)^(-1) = 0.816 → 81.6%

Dies/wafer (5mm die, 300mm wafer) ≈ 5,000
Dies/wafer (15mm die, 300mm wafer) ≈ 330

Cost/die (5mm): $8,000 / (5,000 × 0.976) ≈ $1.64
Cost/die (15mm): $8,000 / (330 × 0.816) ≈ $29.70

Fixed vs Variable Costs

• Fixed: Equipment depreciation, facility → don't scale with utilization below capacity.
• Variable: Materials, labor → scale with wafer starts.
• High utilization (> 85%): Fixed cost per wafer minimized → fabs run at high utilization for economics.
• Low utilization: Fixed costs dominate → fab becomes uneconomical → explains why foundries minimize idle capacity.

Foundry vs IDM Economics

• IDM (Intel, Samsung): Own fabs → high fixed cost → must maintain high utilization across product portfolio.
• Fabless (NVIDIA, Qualcomm) + Foundry (TSMC): Fabless pays per-wafer → no fixed cost → flexible.
• TSMC economics: 90%+ utilization → spreads equipment cost across many customers → efficient.
• Leading-edge foundry margin: TSMC gross margin ~53% → reflects premium for leading-node capacity.

Chiplet Economics

• Large monolithic die: Small yield × limited dies per wafer → high cost.
• Disaggregated chiplets: Each small die → higher yield, more dies/wafer → lower cost per function.
• Packaging cost: Add chiplet assembly cost + substrate cost → net economics favor chiplets at > 400mm² equivalent die size.

Semiconductor cost modeling is the financial lens that makes semiconductor strategy legible — understanding that a 1mm² increase in die area at advanced nodes costs $30–50 per die in additional manufacturing cost explains why tape-out teams obsess over layout density, why chiplet disaggregation makes economic sense at large die sizes, and why TSMC prices leading-edge capacity at a premium that still saves customers money compared to building their own fabs, translating abstract semiconductor physics and manufacturing complexity into the dollars-per-transistor economics that drive the entire $600B semiconductor industry.