<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">The 1T1C DRAM cell: one bit as charge on a tiny capacitor</text><text x="20" y="50" fill="#8b949e" font-size="12.5">A single transistor gates charge onto a capacitor &#8212; dense and cheap, but it leaks and must be refreshed</text><!-- Panel 1: the cell --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 &#183; One transistor, one cap</text><text x="32" y="106" fill="#8b949e" font-size="10.5">the simplest memory cell there is</text><rect x="42" y="118" width="182" height="180" rx="3" fill="#111a24" stroke="#30363d"/><!-- wordline --><line x1="52" y1="140" x2="214" y2="140" stroke="#e0b13a" stroke-width="2"/><text x="150" y="136" fill="#e0b13a" font-size="8">WL (wordline)</text><!-- bitline --><line x1="80" y1="150" x2="80" y2="288" stroke="#38bdf8" stroke-width="1.5"/><text x="60" y="164" fill="#38bdf8" font-size="8">BL</text><!-- access transistor --><rect x="92" y="176" width="20" height="16" rx="2" fill="#6b5fb0"/><line x1="80" y1="184" x2="92" y2="184" stroke="#8b949e" stroke-width="1"/><line x1="102" y1="150" x2="102" y2="176" stroke="#e0b13a" stroke-width="1"/><text x="116" y="188" fill="#c4b5fd" font-size="8">access FET</text><!-- to capacitor --><line x1="112" y1="184" x2="140" y2="184" stroke="#8b949e" stroke-width="1"/><line x1="140" y1="184" x2="140" y2="212" stroke="#8b949e" stroke-width="1"/><!-- capacitor plates --><line x1="120" y1="212" x2="160" y2="212" stroke="#34d399" stroke-width="2.5"/><line x1="120" y1="222" x2="160" y2="222" stroke="#34d399" stroke-width="2.5"/><line x1="140" y1="222" x2="140" y2="240" stroke="#8b949e" stroke-width="1"/><line x1="128" y1="240" x2="152" y2="240" stroke="#8b949e" stroke-width="1.5"/><line x1="132" y1="245" x2="148" y2="245" stroke="#8b949e" stroke-width="1"/><text x="166" y="220" fill="#34d399" font-size="8">C (storage)</text><!-- charge dots --><circle cx="130" cy="217" r="1.6" fill="#f0d9b5"/><circle cx="140" cy="217" r="1.6" fill="#f0d9b5"/><circle cx="150" cy="217" r="1.6" fill="#f0d9b5"/><text x="52" y="268" fill="#8b949e" font-size="7.5">charged = 1, empty = 0</text><text x="52" y="282" fill="#8b949e" font-size="7.5">the cap is a deep trench or tall stack</text><text x="32" y="318" fill="#adb5bd" font-size="9.5">The wordline turns on the transistor,</text><text x="32" y="333" fill="#adb5bd" font-size="9.5">connecting the bitline to the capacitor</text><text x="32" y="348" fill="#adb5bd" font-size="9.5">so charge can flow in or out.</text><!-- Panel 2: operations --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#9fd8ef" font-size="13" font-weight="700">2 &#183; Write, read, refresh</text><text x="279" y="106" fill="#8b949e" font-size="10.5">reading destroys the bit</text><rect x="287" y="118" width="196" height="60" rx="3" fill="#111a24" stroke="#30363d"/><text x="297" y="134" fill="#e0b13a" font-size="9.5" font-weight="700">Write</text><text x="297" y="150" fill="#8b949e" font-size="8.5">raise WL, drive BL high or low; the cap</text><text x="297" y="163" fill="#8b949e" font-size="8.5">charges to that level, then WL closes.</text><rect x="287" y="184" width="196" height="76" rx="3" fill="#111a24" stroke="#30363d"/><text x="297" y="200" fill="#9fd8ef" font-size="9.5" font-weight="700">Read (destructive)</text><text x="297" y="216" fill="#8b949e" font-size="8.5">precharge BL to mid-level, raise WL; the</text><text x="297" y="229" fill="#8b949e" font-size="8.5">cap nudges BL up or down by a few mV.</text><text x="297" y="242" fill="#8b949e" font-size="8.5">A sense amp resolves it &#8212; and must</text><text x="297" y="255" fill="#8b949e" font-size="8.5">write the value back, since the read drained it.</text><rect x="287" y="266" width="196" height="80" rx="3" fill="#111a24" stroke="#30363d"/><text x="297" y="282" fill="#f87171" font-size="9.5" font-weight="700">Refresh</text><text x="297" y="298" fill="#8b949e" font-size="8.5">the cap leaks in milliseconds, so every</text><text x="297" y="311" fill="#8b949e" font-size="8.5">row is read and rewritten thousands of</text><text x="297" y="324" fill="#8b949e" font-size="8.5">times a second. That refresh traffic and</text><text x="297" y="337" fill="#8b949e" font-size="8.5">its power is the price of DRAM density.</text><!-- Panel 3: why / tradeoffs --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#c4b5fd" font-size="13" font-weight="700">3 &#183; Dense, cheap, volatile</text><text x="526" y="106" fill="#8b949e" font-size="10.5">the opposite tradeoff to SRAM</text><circle cx="532" cy="126" r="2.4" fill="#34d399"/><text x="542" y="129" fill="#e6edf3" font-size="10" font-weight="700">Tiny cell = huge capacity</text><text x="542" y="143" fill="#8b949e" font-size="9">one FET + one cap packs far more bits</text><text x="542" y="156" fill="#8b949e" font-size="9">per mm&#178; than SRAM&#8217;s six transistors.</text><circle cx="532" cy="176" r="2.4" fill="#38bdf8"/><text x="542" y="179" fill="#e6edf3" font-size="10" font-weight="700">Slower than SRAM</text><text x="542" y="193" fill="#8b949e" font-size="9">sensing tiny charge takes time; DRAM is</text><text x="542" y="206" fill="#8b949e" font-size="9">main memory, not the on-die cache.</text><circle cx="532" cy="226" r="2.4" fill="#e0b13a"/><text x="542" y="229" fill="#e6edf3" font-size="10" font-weight="700">Scaling the capacitor</text><text x="542" y="243" fill="#8b949e" font-size="9">it must stay big enough to sense even as</text><text x="542" y="256" fill="#8b949e" font-size="9">cells shrink &#8212; hence deep 3D structures.</text><rect x="526" y="272" width="202" height="82" rx="5" fill="#111a24" stroke="#30363d"/><text x="536" y="290" fill="#f87171" font-size="10" font-weight="700">The capacitor is the challenge</text><text x="536" y="306" fill="#adb5bd" font-size="9">To hold enough charge in a shrinking</text><text x="536" y="320" fill="#adb5bd" font-size="9">footprint, makers build tall stacked or</text><text x="536" y="334" fill="#adb5bd" font-size="9">deep trench caps with high-k dielectrics.</text><text x="536" y="348" fill="#adb5bd" font-size="9">This, not the transistor, gates DRAM scaling.</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#34d399" font-size="11" font-weight="700">Charge = the bit</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">A full capacitor is a 1, an empty</text><text x="32" y="440" fill="#adb5bd" font-size="9.5">one is a 0 &#8212; stored as electrons.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#f87171" font-size="11" font-weight="700">Volatile &amp; refreshed</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">Leaks in milliseconds; every row is</text><text x="279" y="440" fill="#adb5bd" font-size="9.5">rewritten constantly to survive.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#38bdf8" font-size="11" font-weight="700">Density over speed</text><text x="526" y="424" fill="#adb5bd" font-size="9.5">The opposite of SRAM &#8212; smaller and</text><text x="526" y="440" fill="#adb5bd" font-size="9.5">cheaper per bit, but slower &amp; volatile.</text></svg>

Semiconductor Memory Technologies are the diverse family of integrated circuit storage devices — from volatile SRAM and DRAM that lose data when power is removed, to non-volatile Flash and emerging memories that retain data indefinitely — each optimized for different combinations of speed, density, endurance, and cost that define the memory hierarchy from processor cache to mass storage.

SRAM (Static RAM):

• 6T Bitcell: two cross-coupled inverters form bistable latch, two access transistors connect to bitlines — data retained as long as power is applied; no refresh required; read by sensing differential voltage on complementary bitlines
• Performance: fastest memory technology — access time 0.5-2 ns; used for L1/L2/L3 caches where speed is critical; operates at full processor clock frequency
• Area Penalty: 6T cell is 100-150× larger than DRAM cell — typical bitcell area: 0.02-0.05 μm² at 7nm node; limits practical SRAM capacity to tens of megabytes on-chip
• Design Challenges: read stability (noise margin), write ability, and hold margin must be simultaneously optimized — cell ratio (pull-down/access transistor ratio) and pull-up ratio determine read/write margins; process variation in minimum-size transistors limits yield

DRAM (Dynamic RAM):

• 1T1C Cell: single access transistor and storage capacitor — charge on capacitor represents stored bit; capacitor charge leaks through transistor sub-threshold current requiring periodic refresh (every 32-64 ms)
• Capacitor Scaling: maintaining >20 fF capacitance as cells shrink below 20 nm pitch — high-k dielectrics (ZrO₂/Al₂O₃/HfO₂ stack), 3D capacitor structures (pillar or cylinder) with aspect ratios >60:1
• Refresh Overhead: each row must be periodically read and rewritten — refresh consumes 10-30% of DRAM bandwidth and power; Row Hammer vulnerability: repeated access to one row disturbs adjacent rows requiring mitigation (TRR, PARA)
• HBM (High Bandwidth Memory): 3D-stacked DRAM with TSVs providing >1 TB/s bandwidth — 4-16 die stack with wide (1024-bit) interface; bonded to logic die or silicon interposer; essential for AI accelerators

Non-Volatile Memory:

• NAND Flash: floating gate or charge trap transistors store data as threshold voltage levels — SLC (1 bit/cell), MLC (2), TLC (3), QLC (4 bits/cell); 3D NAND stacks 100-300 layers vertically for density; program/erase endurance 1K-100K cycles depending on technology
• NOR Flash: random-access read capability at near-DRAM speed — used for code storage (boot ROM) in embedded systems; lower density than NAND but enables execute-in-place (XIP) operation
• MRAM (Magnetoresistive RAM): magnetic tunnel junction stores data as parallel/anti-parallel magnetization — non-volatile, unlimited endurance, SRAM-comparable speed; becoming embedded replacement for SRAM/Flash in MCUs
• ReRAM/PCRAM: resistive switching (filament formation/dissolution) or phase change (crystalline/amorphous) — positioned between DRAM and Flash in the memory hierarchy; Intel Optane used PCRAM before discontinuation

Semiconductor memory technologies collectively form the multi-level memory hierarchy that bridges the enormous speed gap between processors and storage — understanding the fundamental tradeoffs between speed, density, volatility, endurance, and cost is essential for system architects designing the memory subsystems of modern computing platforms.