<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 760 470" font-family="Segoe UI,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Advanced packaging: the landscape of ways to wire many dies as one</text><text x="20" y="50" fill="#8b949e" font-size="12.5">When one big die stops paying off, performance comes from linking separate dies in-package to act like one chip</text><!-- ===== PANEL 1 ===== --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="36" y="92" fill="#38bdf8" font-size="14" font-weight="700">1 · Why package at all</text><text x="132" y="111" text-anchor="middle" fill="#f87171" font-size="8.5">reticle limit ~800 mm²</text><line x1="40" y1="116" x2="224" y2="116" stroke="#f87171" stroke-width="1" stroke-dasharray="4 3"/><rect x="92" y="120" width="80" height="28" rx="3" fill="#1c2733" stroke="#f87171"/><text x="132" y="138" text-anchor="middle" fill="#adb5bd" font-size="10">one big die</text><text x="36" y="170" fill="#adb5bd" font-size="10.5">Two hard walls hit at once:</text><text x="36" y="186" fill="#f0a0a0" font-size="10.5">· reticle — a die can't top ~800 mm²</text><text x="36" y="201" fill="#f0a0a0" font-size="10.5">· memory wall — one die can't feed</text><text x="36" y="214" fill="#f0a0a0" font-size="10.5">  enough HBM to a matrix engine</text><text x="36" y="238" fill="#34d399" font-size="10.5" font-weight="700">The fix: split into chiplets and</text><text x="36" y="252" fill="#34d399" font-size="10.5" font-weight="700">bring the memory into the package</text><rect x="44" y="262" width="176" height="34" rx="3" fill="#3a2c1e" stroke="#5a4632"/><rect x="64" y="268" width="40" height="22" rx="2" fill="#38506a" stroke="#6f8fb0"/><text x="84" y="282" text-anchor="middle" fill="#cfe0ef" font-size="8">HBM</text><rect x="116" y="268" width="32" height="22" rx="2" fill="#233041" stroke="#6f8fb0"/><text x="132" y="282" text-anchor="middle" fill="#cfe0ef" font-size="8">logic</text><rect x="160" y="268" width="40" height="22" rx="2" fill="#38506a" stroke="#6f8fb0"/><text x="180" y="282" text-anchor="middle" fill="#cfe0ef" font-size="8">HBM</text><text x="132" y="312" text-anchor="middle" fill="#8b949e" font-size="9">one package, behaving like one chip</text><!-- ===== PANEL 2 ===== --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="283" y="92" fill="#38bdf8" font-size="14" font-weight="700">2 · The family of techniques</text><!-- 2.5D row --><rect x="283" y="118" width="30" height="5" fill="#38506a"/><rect x="285" y="110" width="12" height="8" rx="1" fill="#233041" stroke="#6f8fb0"/><rect x="300" y="110" width="12" height="8" rx="1" fill="#233041" stroke="#6f8fb0"/><text x="322" y="115" fill="#38bdf8" font-size="10.5" font-weight="700">2.5D — on an interposer</text><text x="322" y="128" fill="#8b949e" font-size="9.3">CoWoS-S/R/L · EMIB · Si bridge</text><!-- Fan-out row --><rect x="285" y="158" width="24" height="7" rx="1" fill="#1c2733" stroke="#6f8fb0"/><rect x="283" y="166" width="28" height="5" fill="#1c1430" stroke="#6b5fb0"/><text x="322" y="160" fill="#34d399" font-size="10.5" font-weight="700">Fan-out — RDL, no substrate</text><text x="322" y="173" fill="#8b949e" font-size="9.3">FOWLP · InFO · FOPLP</text><!-- 3D row --><rect x="287" y="204" width="22" height="6" rx="1" fill="#16332a" stroke="#3f9d6f"/><rect x="287" y="211" width="22" height="6" rx="1" fill="#1c2733" stroke="#3f9d6f"/><text x="322" y="209" fill="#a99cf0" font-size="10.5" font-weight="700">3D — stacked vertically</text><text x="322" y="222" fill="#8b949e" font-size="9.3">TSV stack · Cu-Cu bond · monolithic</text><line x1="283" y1="242" x2="477" y2="242" stroke="#30363d"/><text x="283" y="262" fill="#e0b13a" font-size="10.5" font-weight="700">Coarser → finer die-to-die pitch:</text><text x="283" y="278" fill="#c9d1d9" font-size="9.6">substrate · fan-out · 2.5D · 3D · monolithic</text><text x="283" y="303" fill="#8b949e" font-size="10">Finer pitch buys more bandwidth</text><text x="283" y="317" fill="#8b949e" font-size="10">per edge — and costs more to build.</text><text x="283" y="341" fill="#8b949e" font-size="10">Heterogeneous integration mixes</text><text x="283" y="354" fill="#8b949e" font-size="10">nodes and functions across all three.</text><!-- ===== PANEL 3 ===== --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="530" y="92" fill="#38bdf8" font-size="14" font-weight="700">3 · The shared trade-offs</text><circle cx="535" cy="115" r="3" fill="#38bdf8"/><text x="545" y="118" fill="#38bdf8" font-size="11" font-weight="700">Electrical</text><text x="545" y="132" fill="#adb5bd" font-size="10.3">interconnect pitch sets BW &amp; pJ/bit</text><circle cx="535" cy="152" r="3" fill="#f87171"/><text x="545" y="155" fill="#f87171" font-size="11" font-weight="700">Thermal</text><text x="545" y="169" fill="#adb5bd" font-size="10.3">heat must escape dense/stacked dies</text><circle cx="535" cy="189" r="3" fill="#e0b13a"/><text x="545" y="192" fill="#e0b13a" font-size="11" font-weight="700">Mechanical</text><text x="545" y="206" fill="#adb5bd" font-size="10.3">CTE mismatch → warpage &amp; stress</text><circle cx="535" cy="226" r="3" fill="#34d399"/><text x="545" y="229" fill="#34d399" font-size="11" font-weight="700">Yield &amp; cost</text><text x="545" y="243" fill="#adb5bd" font-size="10.3">known-good-die, test, capacity chain</text><line x1="530" y1="258" x2="724" y2="258" stroke="#30363d"/><text x="530" y="278" fill="#f0d9b5" font-size="11" font-weight="700">Packaging is now as central to</text><text x="530" y="292" fill="#f0d9b5" font-size="11" font-weight="700">performance as the transistor.</text><text x="530" y="315" fill="#8b949e" font-size="10">One coupled electrical–thermal–</text><text x="530" y="329" fill="#8b949e" font-size="10">mechanical–economic system.</text><!-- ===== BOTTOM CARDS ===== --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="36" y="406" fill="#f87171" font-size="12.5" font-weight="700">Two walls forced it</text><text x="36" y="424" fill="#adb5bd" font-size="10">The reticle limit (~800 mm²) and the</text><text x="36" y="437" fill="#adb5bd" font-size="10">memory wall pushed designs off one</text><text x="36" y="450" fill="#adb5bd" font-size="10">monolithic die.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="283" y="406" fill="#e0b13a" font-size="12.5" font-weight="700">Pick by interconnect density</text><text x="283" y="424" fill="#adb5bd" font-size="10">Substrate, fan-out, 2.5D, 3D and</text><text x="283" y="437" fill="#adb5bd" font-size="10">monolithic trade cost for tighter</text><text x="283" y="450" fill="#adb5bd" font-size="10">die-to-die pitch.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="530" y="406" fill="#34d399" font-size="12.5" font-weight="700">Same coupled trade-offs</text><text x="530" y="424" fill="#adb5bd" font-size="10">Every option juggles electrical,</text><text x="530" y="437" fill="#adb5bd" font-size="10">thermal, mechanical, yield and</text><text x="530" y="450" fill="#adb5bd" font-size="10">cost together.</text></svg>

Advanced Semiconductor Packaging is the technology domain that creates the physical and electrical interface between semiconductor die and the system board — evolving from simple wire-bond packages to sophisticated 2.5D/3D architectures with silicon interposers, fan-out redistribution layers, and chiplet integration that increasingly determine system performance and cost.

Fan-Out Wafer-Level Packaging (FOWLP):

• Process: die embedded in epoxy mold compound, redistribution layers (RDL) patterned on the reconstituted wafer surface — fan-out extends I/O beyond die edge, enabling higher pin count than fan-in WLP
• InFO (Integrated Fan-Out): TSMC's FOWLP technology used in Apple A-series and M-series processors — eliminates substrate for thinner package (PoP configuration saves 0.1-0.3 mm); RDL line/space down to 2/2 μm
• eWLB (Embedded Wafer Level Ball Grid Array): Infineon/JCET technology for cost-effective fan-out — 300mm reconstituted wafer process; used in RF front-end modules, PMIC, and baseband processors
• High-Density Fan-Out: fine-pitch RDL (<5 μm L/S) enabling chip-to-chip interconnect within the fan-out package — HDFO competes with silicon interposer for heterogeneous integration at lower cost

2.5D Integration:

• Silicon Interposer: passive silicon die with through-silicon vias (TSVs) and fine-pitch wiring connecting multiple active die — enables high-bandwidth chip-to-chip communication (>1 TB/s for HBM interfaces); TSMC CoWoS leads this segment
• Organic Interposer: organic substrate with fine-pitch wiring replacing silicon — lower cost but coarser feature size (5-10 μm vs. 0.5 μm for silicon); Intel EMIB (Embedded Multi-die Interconnect Bridge) embeds small silicon bridge in organic substrate at chip-to-chip boundaries only
• Glass Interposer: emerging technology using glass core with TGV (through-glass vias) — lower electrical loss than silicon, better dimensional stability than organic; panel-level processing for cost reduction
• Chiplet Assembly: known-good die (KGD) placed on interposer — enables mixing die from different process nodes, foundries, and technologies; yield advantage over monolithic integration for large die

3D Integration:

• Die Stacking: multiple die stacked vertically with TSVs or hybrid bonding for vertical interconnects — HBM (High Bandwidth Memory) stacks 4-16 DRAM die with TSVs achieving 1-1.2 TB/s bandwidth per stack
• Wafer-to-Wafer (W2W): permanent bonding of two processed wafers before dicing — highest density and throughput but requires matched die sizes; used for image sensors (backside illumination) and 3D NAND
• Die-to-Wafer (D2W): individual KGD bonded to a wafer — enables mixing die sizes and avoids compound yield loss (only good die bonded); hybrid bonding at <10 μm pitch achievable
• Thermal Management: 3D stacking concentrates power density — heat must conduct through stacked die; thermal TSVs, microfluidic cooling channels, and thermal interface materials manage the increased thermal resistance

Advanced packaging has become the primary vehicle for continued system performance scaling — as Moore's Law slows, the disaggregation of SoCs into optimally-manufactured chiplets connected through advanced packaging delivers better performance, yield, cost, and time-to-market than monolithic die scaling alone.