Semiconductor Production Testing is the quality assurance process that electrically tests every manufactured die to verify correct functionality and performance — using automated test equipment (ATE) to apply millions of test patterns to each chip, measuring parametric values and functional responses to identify defective die before they are packaged and shipped to customers, where the cost of finding a defect increases 10× at each subsequent integration level (wafer → package → board → system).

Test Economics

A defect found at wafer probe costs ~$0.01-$0.10 (discard the die). Found after packaging: ~$1 (wasted package material + assembly cost). Found at board assembly: ~$10-$100. Found in the field (customer return): ~$1000+ (warranty, reputation damage). This 10× cost multiplication at each level drives the semiconductor industry's massive investment in testing at the earliest possible stage.

Wafer Probe (Sort) Test

• Probe Card: Precision mechanical device with thousands of probe needles that contact every die's bond pads simultaneously. Modern probe cards: >10,000 probes, contact pitch <40 μm, contact force 2-5 grams/probe.
• ATE (Automated Test Equipment): High-speed test systems (Teradyne UltraFlex, Advantest V93000) that generate digital test patterns at GHz rates, measure timing, voltage, and current. Cost: $2-$10 million per ATE system.
• Parallel Testing: Modern ATEs test 8-64 die simultaneously (multi-site testing) to improve throughput and reduce per-die test cost.

Test Methods

• Structural (Scan) Test: Flip-flops in the design are connected in scan chains. Test patterns shift data through scan chains, capture the response, and compare with expected values. Detects stuck-at faults, transition faults, and bridging faults. Fault coverage target: >99% for all detectable faults.
• BIST (Built-In Self-Test): On-chip test logic generates patterns and checks responses autonomously. Memory BIST tests every cell in SRAM/ROM arrays. Logic BIST uses LFSRs to generate pseudo-random patterns. Reduces ATE complexity and test time.
• IDDQ Testing: Measure quiescent supply current. A defect-free CMOS circuit draws near-zero static current (leakage only). A bridging defect or stuck-at fault creates a resistive path, increasing IDDQ. Simple measurement detects shorts and leakage failures.
• At-Speed Test: Apply test patterns at the design's target operating frequency. Detects delay faults (paths that are too slow) that functional-at-reduced-speed testing would miss. Launch-on-shift and launch-on-capture are the two at-speed scan test methods.
• Analog/Mixed-Signal Test: ADC/DAC linearity, PLL lock range and jitter, SerDes eye diagram, RF power and frequency response. Requires specialized ATE instruments (AWGs, digitizers, spectrum analyzers).

Parametric Testing

Before functional testing, measure wafer-level parametric test structures (PCM — Process Control Monitor):

• Transistor Vth, Idsat, Ioff, DIBL
• Sheet resistance of metal layers
• Contact/via resistance
• Capacitance (gate, interconnect)
• Dielectric breakdown voltage

Parametric failures indicate process excursions. Statistical Process Control (SPC) on PCM data catches process drift before it produces defective die.

Test Cost Optimization

Test cost = ATE time × ATE amortization rate. Modern SoCs with billions of transistors require millions of test patterns. Optimizing:

• Test Compression: Compress test patterns 50-200× using on-chip decompressors. Reduces scan chain shift time dramatically.
• Adaptive Test: Reduce test coverage for die from wafers with strong parametric data. Apply full test coverage only to borderline wafers.
• System-Level Test (SLT): Final testing at the system level (running actual software) to catch defects that structural test misses.

Semiconductor Production Testing is the economic filter between fabrication and shipment — the process that converts wafers of mixed-quality die into guaranteed-good products, ensuring that the billions of transistors on each shipped chip meet the performance, power, and reliability specifications promised in the datasheet.