Semiconductor Test and Characterization is the comprehensive suite of electrical measurements performed at wafer level and package level to verify device functionality, parametric performance, and reliability — serving as the final quality gate that ensures only known-good dies reach customers while providing critical feedback for process optimization and yield improvement.

Wafer-Level Testing (Probe):

• Wafer Probe: automated probe stations (FormFactor, Tokyo Electron) contact bond pads or bumps with probe needles or MEMS probe cards; test every die on the wafer before dicing and packaging; probe card with 1000-10,000+ probe tips contacts multiple dies simultaneously
• Probe Card Technology: cantilever, vertical, and MEMS probe cards provide electrical contact to die pads; probe tip diameter 15-25 μm for wire bond pads, <40 μm pitch for flip-chip bumps; contact resistance <1 Ω required; probe card cost $50,000-500,000 for advanced designs
• Sort Testing: functional and parametric tests identify good dies (pass), failed dies (ink/electronic marking), and partially good dies (binning for different speed/power grades); sort yield directly impacts manufacturing cost and profitability
• Multi-Die Probing: testing 8-32 dies simultaneously increases throughput; parallel test requires matched probe card channels and synchronized test patterns; throughput >500 wafers per day for high-volume production

Parametric and Structural Testing:

• Process Control Monitors (PCM): test structures in scribe lines measure transistor parameters (Vt, Idsat, Ioff, gm), resistor values, capacitor characteristics, and interconnect resistance; 50-200 parameters measured per wafer; data feeds statistical process control (SPC) systems
• Transistor Characterization: Id-Vg and Id-Vd curves extracted for NMOS and PMOS at multiple channel lengths and widths; subthreshold swing, DIBL, and mobility extracted; ring oscillator frequency measures circuit-level performance
• Interconnect Testing: via chain resistance (1000-1M vias in series) measures via yield and resistance; comb-serpentine structures detect shorts and opens in metal layers; electromigration test structures assess interconnect reliability
• Capacitance Measurement: MOS capacitor C-V curves characterize gate oxide thickness, interface trap density, and flat-band voltage; MIM capacitor structures verify back-end dielectric properties; precision LCR meters measure fF-level capacitances

Package-Level Testing:

• Final Test: packaged devices tested on automatic test equipment (ATE) — Advantest, Teradyne systems costing $2-10M each; functional test applies input vectors and verifies output responses; speed binning determines maximum operating frequency for each device
• Burn-In: accelerated stress testing at elevated temperature (125°C) and voltage (1.1-1.2× nominal) for 24-168 hours; screens infant mortality failures caused by latent defects; HTOL (high temperature operating life) validates long-term reliability
• System-Level Test (SLT): devices tested in near-application conditions running actual firmware or OS; catches defects missed by structural test patterns; increasingly important for complex SoCs, GPUs, and AI accelerators; test time 30-300 seconds per device
• Known Good Die (KGD): for advanced packaging (chiplets, HBM), individual dies must be fully tested before integration; wafer-level burn-in and comprehensive probe testing ensure KGD quality; defective die in multi-die package wastes all co-packaged good dies

Test Economics and Optimization:

• Test Cost: test represents 5-15% of total chip manufacturing cost; ATE depreciation, probe card consumables, test time, and handler throughput drive cost; reducing test time by 10% can save millions annually for high-volume products
• Design for Test (DFT): scan chains, BIST (built-in self-test), and JTAG boundary scan enable efficient structural testing; scan compression (100-1000× reduction in test data volume) reduces test time; MBIST tests embedded memories with minimal ATE involvement
• Adaptive Testing: machine learning models predict die quality from partial test results; good dies skip redundant tests reducing average test time by 20-40%; wafer-level data (inline metrology, probe results) informs package-level test decisions
• Test Data Analytics: millions of test parameters per wafer analyzed for yield signatures, spatial patterns, and process correlations; outlier detection identifies marginally passing dies that may fail in the field; geographic information system (GIS) visualization reveals wafer-level patterns

Semiconductor test and characterization is the quality assurance backbone of chip manufacturing — in an industry where a single defective chip can cause a vehicle recall or data center outage, comprehensive testing at every stage from wafer to system ensures the extraordinary reliability that modern electronics demand.