Semiconductor Test Program Development is the engineering discipline of creating comprehensive test sequences that exercise every function and fault model of an integrated circuit on automatic test equipment (ATE) — balancing fault coverage (detecting all defective chips), test time (directly determines test cost), and quality metrics (defects per million shipped), where a modern SoC test program may include thousands of test patterns across structural, functional, parametric, and at-speed test categories.

Test Categories

Test Program Structure

[Test Program]
  ├── [DC parametric tests]
  │    ├── Open/short test (contact integrity)
  │    ├── Leakage (IDDQ, junction leakage)
  │    └── Power supply current (IDD at each voltage)
  │
  ├── [Structural tests]
  │    ├── Scan stuck-at (ATPG patterns)
  │    ├── Scan transition-delay (at-speed)
  │    ├── Scan bridge/IDDQ patterns
  │    └── Scan compression patterns
  │
  ├── [Memory BIST]
  │    ├── SRAM MBIST (all embedded memories)
  │    ├── ROM BIST
  │    └── Memory repair (fuse programming)
  │
  ├── [Functional tests]
  │    ├── PLL lock test
  │    ├── IO loopback
  │    ├── Core functionality (processor boot)
  │    └── Interface protocol test (PCIe, USB)
  │
  ├── [At-speed tests]
  │    ├── Clock frequency test (Fmax search)
  │    ├── SHMOO plot (voltage/frequency margin)
  │    └── Speed binning
  │
  └── [Characterization (engineering only)]
       ├── Die-to-die variation mapping
       ├── Temperature sensitivity
       └── Voltage margin testing

ATPG (Automatic Test Pattern Generation)

• ATPG tool (Synopsys TetraMAX, Cadence Modus): Automatically generates test vectors.
• Stuck-at model: Detect any node permanently stuck at 0 or 1.
• Transition model: Detect slow-to-rise or slow-to-fall faults.
• Target: >99.5% fault coverage for high-quality products.
• Pattern count: 1,000-100,000 scan patterns depending on design size.
• Compression: Scan compression (EDT, DFTMAX) reduces pattern count 10-100×.

Test Time and Cost

Test Quality Metrics

Automotive Test Requirements (ISO 26262)

• ASIL-B/C/D: Require LBIST, MBIST, online monitoring.
• DPPM target: <1 (vs. consumer ~10-100).
• Multi-temperature test: -40°C to 150°C.
• Test cost: 2-5× higher than consumer.

Semiconductor test program development is the economic gatekeeper between fabrication and the customer — a well-optimized test program maximizes defect detection while minimizing test time and cost, directly determining both the quality of shipped products and the profitability of semiconductor manufacturing, where the difference between a 1-second and 2-second test program can mean millions of dollars in annual ATE cost for a high-volume product.