SerDes (Serializer/Deserializer) Design is the high-speed I/O circuit design discipline that converts parallel data into a high-speed serial bit stream for transmission over a single differential pair — achieving data rates from 1 Gbps to 224 Gbps per lane, enabling the PCIe, Ethernet, USB, and chip-to-chip interconnects that provide the bandwidth backbone for all modern computing systems.

Why SerDes?

• Parallel interfaces: N wires × moderate speed → pin-count bottleneck, skew between lanes.
• Serial interface: 1 differential pair × very high speed → fewer pins, no inter-lane skew.
• Example: 32-bit parallel bus at 1 GHz = 32 Gbps on 64 wires. SerDes: 32 Gbps on 2 wires.

SerDes Architecture

SerDes Generations

NRZ vs. PAM4

• NRZ (Non-Return-to-Zero): 2 voltage levels → 1 bit/symbol.
• PAM4: 4 voltage levels → 2 bits/symbol → double the data rate at same baud rate.
• PAM4 penalty: 3x worse SNR than NRZ → requires stronger FEC and equalization.
• Above 56 Gbps: PAM4 is standard (NRZ eye is too closed at these speeds).

Key Design Challenges

• Jitter budget: Total jitter must be < 1 UI (unit interval) → at 112 Gbps PAM4: 1 UI = ~18 ps.
• Channel loss: PCB traces + connectors attenuate signal → 20-40 dB loss at Nyquist frequency.
• Equalization: TX FFE pre-compensates for channel loss. RX CTLE + DFE recovers signal from ISI.
• CDR (Clock and Data Recovery): Extract clock from incoming data — critical for achieving low BER.
• Power: 112G SerDes: 5-10 mW/Gbps → a 400G port (4 lanes) consumes 2-4W.

SerDes design is the enabling technology for all high-bandwidth digital communication — from the PCIe links connecting GPUs to CPUs, to the Ethernet backbone of data centers, to the chip-to-chip links in chiplet architectures, SerDes circuits are the critical I/O interfaces that determine system bandwidth.