<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,sans-serif">
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  <text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">SerDes — High-Speed Serial Link</text>
  <text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">serialize parallel data, send over a differential pair at 112+ Gbps, recover clock and data at the receiver</text>

  <!-- === TOP: TX → Channel → RX link diagram === -->
  <text x="380" y="72" fill="#e6edf3" font-size="12" font-weight="600" text-anchor="middle">Link Architecture (one lane)</text>

  <!-- TX block -->
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  <text x="122" y="100" fill="#93c5fd" font-size="10" text-anchor="middle" font-weight="600">Transmitter (TX)</text>

  <!-- TX internals -->
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  <text x="72" y="121" fill="#8b98a5" font-size="7.5" text-anchor="middle">Serializer</text>
  <rect x="42" y="132" width="60" height="20" rx="2" fill="#0f1a2a" stroke="#3b82f6" stroke-width="0.7"/>
  <text x="72" y="145" fill="#8b98a5" font-size="7.5" text-anchor="middle">Encoder</text>
  <rect x="42" y="156" width="60" height="20" rx="2" fill="#0f1a2a" stroke="#3b82f6" stroke-width="0.7"/>
  <text x="72" y="169" fill="#8b98a5" font-size="7.5" text-anchor="middle">PLL (clock)</text>

  <!-- TX EQ -->
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  <text x="157" y="125" fill="#6ee7b7" font-size="8.5" text-anchor="middle">TX Equalization</text>
  <text x="157" y="138" fill="#8b98a5" font-size="7.5" text-anchor="middle">FFE (pre/post cursor)</text>
  <text x="157" y="148" fill="#6b7684" font-size="7" text-anchor="middle">3-7 taps</text>

  <!-- Driver -->
  <rect x="115" y="156" width="85" height="20" rx="2" fill="#2a1a0a" stroke="#f59e0b" stroke-width="0.8"/>
  <text x="157" y="169" fill="#fbbf24" font-size="7.5" text-anchor="middle">Driver (diff pair)</text>
  <text x="157" y="192" fill="#6b7684" font-size="7.5" text-anchor="middle">Vswing: 400-800 mVppd</text>

  <!-- Channel (the wire) -->
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  <!-- Channel loss squiggles -->
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  <text x="297" y="133" fill="#fca5a5" font-size="8" text-anchor="middle">Channel</text>
  <text x="297" y="160" fill="#8b98a5" font-size="7.5" text-anchor="middle">PCB trace + connector</text>
  <text x="297" y="172" fill="#f87171" font-size="7.5" text-anchor="middle">loss: -20 to -40 dB @ Nyquist</text>
  <text x="297" y="184" fill="#6b7684" font-size="7" text-anchor="middle">ISI + crosstalk + noise</text>

  <!-- RX block -->
  <rect x="380" y="84" width="200" height="120" rx="6" fill="#080d14" stroke="#a78bfa" stroke-width="1.3"/>
  <text x="480" y="100" fill="#c4b5fd" font-size="10" text-anchor="middle" font-weight="600">Receiver (RX)</text>

  <!-- RX internals -->
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  <text x="434" y="120" fill="#c4b5fd" font-size="8" text-anchor="middle">CTLE (analog EQ)</text>
  <text x="434" y="132" fill="#8b98a5" font-size="7" text-anchor="middle">peaking filter</text>

  <rect x="392" y="142" width="85" height="30" rx="3" fill="#1a1520" stroke="#a78bfa" stroke-width="1"/>
  <text x="434" y="154" fill="#c4b5fd" font-size="8" text-anchor="middle">DFE (digital EQ)</text>
  <text x="434" y="166" fill="#8b98a5" font-size="7" text-anchor="middle">feedback taps</text>

  <rect x="490" y="108" width="78" height="20" rx="2" fill="#0f2a1f" stroke="#34d399" stroke-width="0.7"/>
  <text x="529" y="121" fill="#6ee7b7" font-size="7.5" text-anchor="middle">CDR (clock rec)</text>

  <rect x="490" y="132" width="78" height="20" rx="2" fill="#0f1a2a" stroke="#60a5fa" stroke-width="0.7"/>
  <text x="529" y="145" fill="#93c5fd" font-size="7.5" text-anchor="middle">Deserializer</text>

  <rect x="490" y="156" width="78" height="20" rx="2" fill="#0f1a2a" stroke="#60a5fa" stroke-width="0.7"/>
  <text x="529" y="169" fill="#93c5fd" font-size="7.5" text-anchor="middle">Decoder</text>

  <text x="480" y="196" fill="#6b7684" font-size="7.5" text-anchor="middle">adapt EQ coefficients via training/LMS</text>

  <!-- Arrows TX→Channel→RX -->
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  <polygon points="376,140 382,143 376,146" fill="#a78bfa"/>

  <!-- === RIGHT: Eye diagram === -->
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  <text x="662" y="100" fill="#e6edf3" font-size="9" text-anchor="middle" font-weight="600">Eye Diagram</text>

  <!-- Eye shape (NRZ) -->
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  <path d="M615,145 C630,175 650,175 662,145 C674,175 694,175 710,145" fill="none" stroke="#34d399" stroke-width="1.2" opacity="0.6"/>
  <!-- More traces -->
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  <path d="M615,145 C632,170 648,170 662,145" fill="none" stroke="#34d399" stroke-width="0.6" opacity="0.3"/>

  <!-- Eye height/width annotations -->
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  <text x="670" y="135" fill="#fbbf24" font-size="6.5">height</text>
  <line x1="640" y1="145" x2="685" y2="145" stroke="#60a5fa" stroke-width="0.5" stroke-dasharray="2,1"/>
  <text x="690" y="143" fill="#60a5fa" font-size="6.5">width</text>

  <text x="662" y="188" fill="#8b98a5" font-size="7.5" text-anchor="middle">open eye = good signal</text>
  <text x="662" y="200" fill="#6b7684" font-size="7" text-anchor="middle">BER target: 10^-12</text>

  <!-- === BOTTOM LEFT: PAM4 signaling === -->
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  <text x="190" y="233" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">NRZ vs PAM4 Signaling</text>

  <!-- NRZ (2 levels) -->
  <text x="60" y="253" fill="#34d399" font-size="9">NRZ (2 levels):</text>
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  <text x="130" y="268" fill="#6b7684" font-size="8">1 bit/symbol</text>
  <text x="130" y="280" fill="#6b7684" font-size="7.5">up to 56 Gbps/lane</text>

  <!-- PAM4 (4 levels) -->
  <text x="60" y="298" fill="#fbbf24" font-size="9">PAM4 (4 levels):</text>
  <path d="M60,302 L60,312 L70,312 L70,306 L80,306 L80,302 L90,302 L90,312 L100,312 L100,308 L115,308" fill="none" stroke="#fbbf24" stroke-width="1.2"/>
  <text x="130" y="310" fill="#6b7684" font-size="8">2 bits/symbol</text>
  <text x="130" y="322" fill="#6b7684" font-size="7.5">112 Gbps/lane (same baud)</text>
  <text x="255" y="298" fill="#f87171" font-size="8">trade-off: 3x SNR penalty</text>
  <text x="255" y="310" fill="#8b98a5" font-size="7.5">needs stronger EQ + FEC</text>

  <!-- === BOTTOM RIGHT: Protocols === -->
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  <text x="547" y="233" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">Where SerDes Lives</text>

  <text x="385" y="253" fill="#76b900" font-size="9">NVLink 5: 100G PAM4 (1.8 TB/s/GPU)</text>
  <text x="385" y="269" fill="#60a5fa" font-size="9">PCIe 6.0: 64 GT/s PAM4 (128 GB/s x16)</text>
  <text x="385" y="285" fill="#c4b5fd" font-size="9">Ethernet 800G: 8×112G lanes</text>
  <text x="385" y="301" fill="#fbbf24" font-size="9">HBM3e PHY: 9.6 Gbps/pin, 1024 pins</text>
  <text x="385" y="317" fill="#8b98a5" font-size="9">USB4: 40 Gbps, CXL 3.0: 64 GT/s</text>

  <!-- Key specs -->
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  <text x="380" y="343" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">Design Challenges at 112+ Gbps</text>
  <text x="50" y="361" fill="#8b98a5" font-size="9">Channel loss compensation (40+ dB) · Clock jitter (< 100 fs RMS) · Power: 3-7 pJ/bit</text>
  <text x="50" y="375" fill="#6b7684" font-size="8.5">Process: 5nm FinFET for 224G SerDes · Die area: ~1mm² per lane · PHY IP vendors: Synopsys, Cadence, Alphawave</text>

  <!-- Bottom insight -->
  <text x="380" y="405" fill="#e6edf3" font-size="9.5" text-anchor="middle" font-weight="600">AI cluster bandwidth: 400K+ SerDes lanes in a 10K-GPU cluster — each lane doing analog signal processing at GHz rates</text>

  <text x="380" y="435" fill="#8b98a5" font-size="9" text-anchor="middle">Every bit moved between chips crosses a SerDes — it's analog RF engineering hidden inside digital systems.</text>

  <text x="380" y="460" fill="#6b7684" font-size="11" text-anchor="middle">SerDes is the nervous system between chips — without it, GPUs can't talk, memory can't feed, and AI stops.</text>
</svg>
```SerDes (Serializer/Deserializer)** is the circuit that converts a wide bundle of parallel bits into a single high-speed serial stream for transmission, and back again at the far end. The **PHY** (physical layer) is the broader analog/mixed-signal block that contains the SerDes plus everything needed to actually push bits onto a wire and recover them: line drivers, equalizers, clock recovery, and encoding. Nearly every fast link in modern computing — PCIe, Ethernet, USB, HBM interfaces, and die-to-die chiplet links — is built on SerDes/PHY blocks. They are where the digital world meets the messy physics of real channels, and increasingly where the hardest chip-design problems live.\n\n```svg\n<svg viewBox="0 0 700 348" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,sans-serif">\n  <rect x="0" y="0" width="700" height="348" fill="#0d1117"/>\n  <text x="350" y="28" fill="#e6edf3" font-size="20" font-weight="700" text-anchor="middle">SerDes &amp; the PHY — Wide-and-Slow to Narrow-and-Fast</text>\n  <text x="350" y="49" fill="#8b98a5" font-size="13" text-anchor="middle">turn many parallel bits into one blazing serial stream, then recover it after a lossy channel</text>\n  <rect x="30" y="124" width="64" height="52" rx="6" fill="#141a2e" stroke="#818cf8" stroke-width="1.4"/>\n  <line x1="40" y1="134" x2="84" y2="134" stroke="#a5b4fc" stroke-width="2"/>\n  <line x1="40" y1="145" x2="84" y2="145" stroke="#a5b4fc" stroke-width="2"/>\n  <line x1="40" y1="156" x2="84" y2="156" stroke="#a5b4fc" stroke-width="2"/>\n  <line x1="40" y1="167" x2="84" y2="167" stroke="#a5b4fc" stroke-width="2"/>\n  <text x="62" y="194" fill="#8b98a5" font-size="13" text-anchor="middle">parallel bits</text>\n  <rect x="110" y="128" width="74" height="44" rx="6" fill="#2a1420" stroke="#fbbf24" stroke-width="1.4"/>\n  <text x="147" y="148" fill="#fcd34d" font-size="12" font-weight="700" text-anchor="middle">SER</text>\n  <text x="147" y="162" fill="#8b98a5" font-size="12" text-anchor="middle">to serial</text>\n  <line x1="94" y1="150" x2="110" y2="150" stroke="#3f5169" stroke-width="1.5"/>\n  <path d="M103 153 L110 150 L103 147" stroke="#3f5169" stroke-width="1.5" fill="none"/>\n  <rect x="200" y="128" width="66" height="44" rx="6" fill="#0f1c17" stroke="#34d399" stroke-width="1.4"/>\n  <text x="233" y="148" fill="#6ee7b7" font-size="12" font-weight="700" text-anchor="middle">driver</text>\n  <text x="233" y="162" fill="#8b98a5" font-size="12" text-anchor="middle">+ pre-emph</text>\n  <line x1="184" y1="150" x2="200" y2="150" stroke="#3f5169" stroke-width="1.5"/>\n  <path d="M193 153 L200 150 L193 147" stroke="#3f5169" stroke-width="1.5" fill="none"/>\n  <text x="330" y="110" fill="#f87171" font-size="12" text-anchor="middle">lossy channel (PCB / cable)</text>\n  <polyline points="266,150 271,157 276,160 281,158 287,152 292,145 297,142 302,142 307,147 312,153 317,157 322,158 328,154 333,149 338,145 343,143 348,145 353,149 358,154 364,156 369,155 374,152 379,148 384,145 389,145 394,148 399,151 405,154 410,154 415,153 420,150" fill="none" stroke="#f87171" stroke-width="1.6" opacity="0.8"/>\n  <text x="343" y="184" fill="#6b7684" font-size="12" text-anchor="middle">attenuates &amp; smears signal</text>\n  <rect x="420" y="128" width="74" height="44" rx="6" fill="#101826" stroke="#38bdf8" stroke-width="1.4"/>\n  <text x="457" y="146" fill="#7dd3fc" font-size="12" font-weight="700" text-anchor="middle">EQ</text>\n  <text x="457" y="161" fill="#8b98a5" font-size="12" text-anchor="middle">CTLE / DFE + CDR</text>\n  <rect x="510" y="128" width="74" height="44" rx="6" fill="#2a1420" stroke="#fbbf24" stroke-width="1.4"/>\n  <text x="547" y="148" fill="#fcd34d" font-size="12" font-weight="700" text-anchor="middle">DES</text>\n  <text x="547" y="162" fill="#8b98a5" font-size="12" text-anchor="middle">to parallel</text>\n  <line x1="494" y1="150" x2="510" y2="150" stroke="#3f5169" stroke-width="1.5"/>\n  <path d="M503 153 L510 150 L503 147" stroke="#3f5169" stroke-width="1.5" fill="none"/>\n  <rect x="600" y="124" width="64" height="52" rx="6" fill="#141a2e" stroke="#818cf8" stroke-width="1.4"/>\n  <line x1="610" y1="134" x2="654" y2="134" stroke="#a5b4fc" stroke-width="2"/>\n  <line x1="610" y1="145" x2="654" y2="145" stroke="#a5b4fc" stroke-width="2"/>\n  <line x1="610" y1="156" x2="654" y2="156" stroke="#a5b4fc" stroke-width="2"/>\n  <line x1="610" y1="167" x2="654" y2="167" stroke="#a5b4fc" stroke-width="2"/>\n  <text x="632" y="194" fill="#8b98a5" font-size="13" text-anchor="middle">parallel bits</text>\n  <text x="140" y="98" fill="#34d399" font-size="12" font-weight="700">TX (serialize)</text>\n  <text x="470" y="98" fill="#38bdf8" font-size="12" font-weight="700">RX (recover + deserialize)</text>\n  <rect x="159.0" y="272.0" width="82" height="72" rx="6" fill="#0b1220" stroke="#233043" stroke-width="1"/>\n  <path d="M165.0 296.92 Q 200 294.5 235.0 296.92" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 303.08 Q 200 305.5 235.0 303.08" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 296.48 Q 200 294.5 235.0 296.48" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 303.52 Q 200 305.5 235.0 303.52" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 296.04 Q 200 294.5 235.0 296.04" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 303.96 Q 200 305.5 235.0 303.96" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 295.6 Q 200 294.5 235.0 295.6" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 304.4 Q 200 305.5 235.0 304.4" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 295.16 Q 200 294.5 235.0 295.16" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 304.84 Q 200 305.5 235.0 304.84" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 294.72 Q 200 294.5 235.0 294.72" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 305.28 Q 200 305.5 235.0 305.28" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 294.28 Q 200 294.5 235.0 294.28" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <path d="M165.0 305.72 Q 200 305.5 235.0 305.72" fill="none" stroke="#f87171" stroke-width="1" opacity="0.5"/>\n  <text x="200" y="340.0" fill="#f87171" font-size="12" text-anchor="middle">before EQ: eye closed</text>\n  <rect x="289.0" y="272.0" width="82" height="72" rx="6" fill="#0b1220" stroke="#233043" stroke-width="1"/>\n  <path d="M295.0 296.92 Q 330 278.0 365.0 296.92" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 303.08 Q 330 322.0 365.0 303.08" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 296.48 Q 330 278.0 365.0 296.48" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 303.52 Q 330 322.0 365.0 303.52" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 296.04 Q 330 278.0 365.0 296.04" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 303.96 Q 330 322.0 365.0 303.96" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 295.6 Q 330 278.0 365.0 295.6" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 304.4 Q 330 322.0 365.0 304.4" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 295.16 Q 330 278.0 365.0 295.16" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 304.84 Q 330 322.0 365.0 304.84" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 294.72 Q 330 278.0 365.0 294.72" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 305.28 Q 330 322.0 365.0 305.28" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 294.28 Q 330 278.0 365.0 294.28" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <path d="M295.0 305.72 Q 330 322.0 365.0 305.72" fill="none" stroke="#34d399" stroke-width="1" opacity="0.5"/>\n  <text x="330" y="340.0" fill="#34d399" font-size="12" text-anchor="middle">after EQ: eye open</text>\n  <text x="70" y="272" fill="#cbd5e1" font-size="13" font-weight="700">The eye diagram = signal health</text>\n  <rect x="430" y="272" width="234" height="60" rx="6" fill="#0b1220" stroke="#233043" stroke-width="1.4"/>\n  <text x="446" y="290" fill="#cbd5e1" font-size="12" font-weight="700">NRZ vs PAM4</text>\n  <text x="446" y="306" fill="#8b98a5" font-size="13">NRZ: 2 levels = 1 bit/symbol</text>\n  <text x="446" y="320" fill="#8b98a5" font-size="13">PAM4: 4 levels = 2 bits/symbol (Gen6, 224G)</text>\n</svg>\n```\n\n**The core idea is trading width for speed.** Routing 64 parallel wires across a board at a modest clock is expensive in pins, area, and skew — the wires drift out of alignment. A SerDes instead sends the data over one differential pair at a very high rate, so a link needs only a couple of wires per lane. Fewer pins and connectors, at the cost of running the serial line at multi-gigahertz to tens-of-gigahertz symbol rates. This is the trade every high-speed interconnect makes.\n\n**Real channels destroy the signal, so the PHY spends most of its effort undoing that.** A PCB trace or cable attenuates high frequencies and smears each symbol into its neighbors (inter-symbol interference). By the time the signal reaches the receiver, its "eye" — the open region in an overlaid plot of many bit transitions — can be almost completely closed. The PHY fights back with equalization: transmit pre-emphasis/FFE that boosts high frequencies before sending, and receive CTLE and DFE that flatten and cancel the channel's distortion. Good equalization is what re-opens the eye.\n\n**The eye diagram is the universal measure of link health.** Overlaying many received bit periods produces an "eye"; a wide-open eye means the receiver can cleanly distinguish 1s from 0s with timing and voltage margin, while a closed eye means errors. Nearly all SerDes bring-up, characterization, and debugging revolves around opening and measuring the eye, and every equalization knob is tuned to widen it.\n\n**The receiver must recover the clock, because none is sent.** High-speed serial links do not ship a separate clock wire; instead a clock-data recovery (CDR) circuit extracts timing directly from the data transitions and locks onto it. This is why line coding (like 8b/10b or 128b/130b scrambling) matters — it guarantees enough transitions for the CDR to stay locked and keeps the signal DC-balanced.\n\n**Pushing past ~50 Gbps per lane forced a move to PAM4.** Simple on/off (NRZ) signaling sends one bit per symbol; to keep doubling rates without doubling frequency, modern SerDes use PAM4, which encodes two bits per symbol using four voltage levels. That squeezes more data through the same channel bandwidth but shrinks the vertical eye and demands far more sophisticated equalization and error correction — which is why 112G and 224G SerDes are among the most challenging analog blocks on a leading-edge chip.\n\n| Element | Job | Lives in |\n|---|---|---|\n| Serializer / Deserializer | parallel ↔ serial conversion | TX / RX |\n| Driver + FFE/pre-emphasis | shape signal before the channel | TX PHY |\n| CTLE / DFE equalizers | undo channel loss & ISI | RX PHY |\n| CDR | recover the clock from data | RX PHY |\n| Encoding (NRZ / PAM4) | bits-per-symbol & DC balance | both |\n\nRead SerDes/PHY through a *fight-the-channel* lens rather than a *wire* lens: the serializer is the easy part; the real engineering is recovering a clean stream after a lossy trace has done its worst. Almost the entire PHY — pre-emphasis, CTLE, DFE, CDR, FEC — exists to re-open an eye that physics keeps trying to close, and it is exactly this analog battle that sets the practical ceiling on how fast PCIe, Ethernet, and chiplet links can run.\n