High-Speed SerDes Design creates multi-gigabit serial transceivers converting parallel data to high-speed serial streams, using equalization, clock recovery, and signal processing for reliable transmission at 10-200+ Gbps per lane.
Architecture:
| Block | TX | RX |
|---|---|---|
| Data path | Serializer (MUX) | Deserializer (DEMUX) |
| Equalization | FFE | CTLE + DFE |
| Clocking | PLL | CDR |
| Driver/Receiver | Current-mode | Linear EQ front-end |
| Adaptation | TX preset optimization | Eye monitor + loops |
Signaling Evolution:
| Standard | Rate | Modulation | Loss | Application |
|---|---|---|---|---|
| PCIe 5.0 | 32 GT/s | NRZ | ~30 dB | CPU-GPU |
| PCIe 6.0 | 64 GT/s | PAM4 | ~36 dB | CPU-CXL |
| 112G Ethernet | 112 Gbps | PAM4 | ~30 dB | Data center |
| 224G Ethernet | 224 Gbps | PAM4 | ~36 dB | Next-gen DC |
PAM4: 4 voltage levels encoding 2 bits/symbol. ~9.5dB SNR penalty versus NRZ. TX requires precise level spacing; RX typically ADC-based with digital EQ at 100+ Gbps.
Equalization: TX FFE — 2-5 tap FIR pre-distortion compensating channel loss; RX CTLE — analog high-frequency boost; RX DFE — decision feedback canceling post-cursor ISI without noise amplification; ADC-DSP RX — 6-8 bit ADCs with 20+ digital taps, enabling MLSE and ML-based equalization.
CDR: Bang-bang or linear phase detectors driving digital loop filter controlling fractional-N PLL. Jitter tolerance and transfer characteristics are critical specs.
SerDes design operates at the intersection of RF circuit design, signal processing, and digital communication — each speed generation pushes closer to the Shannon limit of copper channels.
Explore 500+ Semiconductor & AI Topics
From EUV lithography to CUDA optimization — search the full knowledge base or chat with our AI assistant.