Shallow Trench Isolation (STI) is the fundamental CMOS isolation technique that electrically separates adjacent transistors by etching shallow trenches (200-400 nm deep) into the silicon substrate and filling them with deposited silicon dioxide — replacing the older LOCOS (Local Oxidation of Silicon) process and enabling the tight transistor pitches required at 250nm and below by eliminating the lateral bird's beak encroachment that limited LOCOS scaling.

Why Isolation Is Necessary

Without isolation, adjacent NMOS and PMOS transistors would share the silicon substrate, creating parasitic current paths (latch-up via parasitic thyristor action), threshold voltage shifts from neighboring well bias, and uncontrolled leakage between devices. Every transistor pair on the chip must be electrically isolated to function independently.

STI Process Flow

1. Pad Oxide and Nitride Deposition: A thin SiO2 pad oxide (~10 nm) is thermally grown, followed by a LPCVD Si3N4 film (~100 nm). The nitride serves as the CMP stop layer and the oxidation mask. 2. Trench Etch: Lithography defines the isolation regions. An anisotropic plasma etch (HBr/Cl2/O2 chemistry) etches through the nitride, pad oxide, and ~300 nm into the silicon. Trench sidewall angle is controlled to ~85-88° (slightly tapered for void-free fill). 3. Liner Oxidation: A thin thermal oxide (~5-10 nm) is grown on the trench sidewalls and bottom. This rounds the trench corners (preventing electric field concentration that would cause junction leakage) and repairs etch-induced surface damage. 4. Trench Fill: High-density plasma CVD (HDP-CVD) or sub-atmospheric CVD (SACVD) deposits SiO2 to completely fill the trench. For narrow trenches at advanced nodes, flowable CVD (FCVD) oxide enables void-free fill at aspect ratios >10:1. 5. CMP Planarization: Chemical-mechanical polishing removes the excess oxide above the trench, stopping on the nitride layer. The result is a perfectly planar surface with oxide-filled trenches flush with the silicon active areas. 6. Nitride Strip: The CMP stop nitride is removed by hot phosphoric acid, leaving the active silicon areas slightly elevated above the STI oxide surface.

Advanced Node Challenges

• Stress Engineering: The STI oxide exerts compressive stress on the adjacent silicon, affecting transistor mobility. At 28nm and below, the magnitude of STI stress is a design variable — closely-spaced transistors experience different stress than isolated ones (the well-known STI stress proximity effect). SPICE models include STI stress corrections.
• Divot Formation: During nitride strip and subsequent wet cleans, the STI oxide at the trench edge can recess below the silicon surface, creating divots that cause gate wrap-around leakage. Divot-free processing requires careful control of every wet chemistry step.

Shallow Trench Isolation is the invisible boundary that gives every transistor its own electrical territory — without it, the billions of devices on a modern chip would interact chaotically, and digital logic as we know it would be impossible.