Shallow Trench Isolation (STI) is the fundamental CMOS process module that electrically isolates adjacent transistors by etching narrow trenches into the silicon substrate and filling them with dielectric (SiO₂) — replacing the older LOCOS (Local Oxidation of Silicon) isolation at the 250 nm node and remaining the standard isolation method through every subsequent generation, where STI trench dimensions have scaled from hundreds of nanometers to sub-15 nm widths at the 3 nm node, creating extreme aspect ratios that challenge dielectric fill quality and introduce stress-mediated effects on device performance.
STI Process Flow
1. Pad Oxide and Nitride: Grow thin SiO₂ pad oxide (~5-10 nm) followed by Si₃N₄ hardmask (~50-80 nm) by LPCVD.
2. Trench Patterning: Lithography defines active (transistor) areas. The surrounding field regions will become isolation trenches.
3. Trench Etch: Anisotropic RIE etches through the SiN hardmask, pad oxide, and into Si substrate. Trench depth: 200-400 nm. Trench width: as narrow as 12-20 nm at advanced nodes. Profile: slightly tapered (85-88° sidewall angle) for better fill.
4. Liner Oxidation: Thin thermal oxide (~3-5 nm) grown on trench sidewalls and bottom. Repairs etch damage to the Si surface and rounds the top/bottom corners (reducing electric field concentration).
5. Trench Fill: Deposit SiO₂ to fill the trench completely:
- HARP (High Aspect Ratio Process): SACVD TEOS/O₃ for good gap fill at moderate AR.
- FCVD (Flowable CVD): Liquid-like SiO₂ precursor flows into narrow trenches and cures in place. Critical for AR >10:1 at advanced nodes.
- HDPCVD: Simultaneous deposition and sputter for void-free fill at moderate AR.
6. CMP Planarization: Chemical-mechanical polish removes excess SiO₂ above the trenches, stopping on the SiN hardmask. Post-CMP surface must be globally planar to ±5-10 nm for subsequent lithography.
7. SiN Strip: Hot phosphoric acid removes the SiN hardmask, leaving STI oxide flush with or slightly recessed relative to the silicon surface.
STI Scaling Challenges
- Gap Fill: At 3 nm node, STI trench width <20 nm with depth ~250 nm → AR >12:1. Conventional CVD cannot fill without voids or seams. FCVD is essential but produces lower-quality oxide (more porous, higher wet etch rate) requiring post-deposition curing (UV, thermal, or steam anneal).
- STI Recess: After CMP and subsequent wet cleans, the STI oxide recesses below the Si surface. Excessive recess exposes the fin sidewall (in FinFET), increasing parasitic leakage at the fin base. Recess control: ±2-3 nm.
- Corner Rounding: Sharp corners at the Si/STI interface create high electric fields that cause parasitic leakage and threshold voltage distortion (hump effect). Liner oxidation rounds corners, but the thermal budget must be minimized at advanced nodes.
Stress Effects
STI oxide induces compressive stress on the enclosed silicon active area:
- The thermal expansion mismatch between SiO₂ and Si creates stress during cool-down from processing temperatures.
- Compressive stress in the channel direction enhances PMOS mobility but degrades NMOS mobility.
- Narrow active areas experience more stress (more STI boundary relative to area) — the "narrow width effect" that shifts Vth and mobility.
- Stress-aware TCAD simulation is required to model these effects for accurate circuit design.
STI is the invisible wall between every transistor on a chip — the isolation structure whose depth, width, fill quality, and stress characteristics directly impact both the electrical isolation that prevents cross-talk and the mechanical effects that alter every transistor's threshold voltage and drive current.