Read SiC dry etching through a plasma-physics and etch-rate/selectivity lens rather than a wet-chemistry lens. Silicon carbide's lattice is locked together by Si–C covalent bonds with a dissociation energy near 4.5 eV, placing it second only to diamond among semiconductors and making SiC chemically inert to virtually every liquid etchant available at room temperature. The only wet-chemistry route with any measurable attack rate on crystalline SiC is molten KOH at roughly 500 °C, which opens crystal-plane-selective pits on the carbon and silicon faces but cannot deliver the anisotropy or aspect ratio that trench MOSFET and power Schottky fabrication demands. Every production-relevant patterning step therefore relies on inductively coupled plasma reactive-ion etching, where plasma physics rather than solvation thermodynamics governs selectivity, etch rate, and sidewall geometry. The critical insight is that an ICP source operating at 13.56 MHz with powers from 1 kW to 3 kW generates a high-density fluorine-radical and argon-ion plasma independently of the bias voltage applied at the substrate chuck, so ion energy and plasma density are separately tunable — a freedom that is essential for a material as chemically resistant as SiC. SF₆ dissociates in the discharge to yield F radicals that attack surface Si atoms, forming volatile SiF₄; O₂ co-feed burns carbon residue and regenerates additional F via intermediate dissociation fragments, while Ar provides directional sputtering momentum that opens the etch front and clears passivating SiOFₓ films from trench bottoms. Silicon carbide's Si–C bond energy of 4.5 eV demands plasma-chemistry energies completely inaccessible to wet etchants, which is the single materials fact that makes ICP-RIE the mandatory patterning route for every power-device trench and mesa structure. Because generating sufficient F radical flux and Ar⁺ ion current requires electron densities an order of magnitude higher than parallel-plate RIE can sustain, ICP sources delivering 1 kW to 3 kW of inductive power are the industry standard for SiC etching. SF₆ is the primary etch gas because each molecule, on electron-impact dissociation, releases up to six F radicals that chemisorb onto surface Si atoms and produce volatile SiF₄, while the carbon co-product must be managed separately by the O₂ addition to avoid a self-poisoning graphitic micro-mask. A crucial consequence is that omitting O₂ from the feed causes carbon to accumulate at the etch front within seconds, producing a pillared, rough surface that degrades etch rate by 60% or more and is incompatible with device geometry requirements. Adding O₂ at 15–25% of the SF₆ molar flow combusts the carbon deposit as CO₂ or COF₂ and concurrently amplifies F* concentration, so the SF₆:O₂ ratio is the single most sensitive recipe knob for controlling etch rate and surface roughness simultaneously. Argon at 10–30% of total flow contributes physical sputtering that prevents RIE lag — the phenomenon by which dense trench arrays etch more slowly than isolated features because passivating SiOFₓ film accumulates faster than ion bombardment removes it in narrow geometries — and Ar flow adjustment is the primary tool for lag compensation without changing etch rate. The Ni hard mask provides etch selectivity of 50 × to 100 × over SiC, enabling trench depths of 10 µm for gate recesses in trench MOSFETs and up to 30 µm for deep-mesa power diode pillars, depths that would erode any photoresist mask entirely before the target depth was reached. Bias voltage independently set from 50 V to 300 V at the substrate electrode controls ion directionality and sidewall angle, with higher bias driving sidewall angles from 80° toward 90° at the cost of increased mask erosion and shallow near-surface crystal damage extending 20 nm to 50 nm below the etch front. The etch behavior of 4H-SiC, with its 3.26 eV bandgap, differs measurably from 6H-SiC at 3.0 eV because differences in near-surface atomic coordination and dangling-bond density alter the fluorine chemisorption rate, and 4H-SiC is exclusively preferred for high-voltage power devices because of its higher electron mobility and more favorable critical field. The parameter space for SiC ICP-RIE is wide but the manufacturable process window is narrow; small drifts in gas ratio or bias power produce measurable changes in etch profile, mask erosion, and sidewall angle. The table below maps representative input variables onto etch rate, selectivity, and profile outcome across six operating points drawn from process-development literature and tool-vendor application data. NIST-traceable gas-flow calibration and pressure metrology are prerequisites for cross-tool recipe transfer, and every chamber should be re-baselined after any maintenance event that touches the RF match network, gas delivery manifold, or chamber liner.

flowchart TD
    A[SiC wafer prep: solvent clean + RCA] --> B[Ni hard mask deposition: sputter or electroplate 200 nm]
    B --> C[Photolithography: coat, expose, develop resist on Ni]
    C --> D[Ni pattern transfer: wet etch or Cl-RIE into Ni film]
    D --> E[ICP-RIE etch: SF6 plus O2 plus Ar at 1-3 kW, 50-300 V bias]
    E --> F{Etch mode?}
    F -->|Bosch| G[Alternate etch and SiOFx passivation cycles: 10-30 s each]
    F -->|Continuous| H[Steady SF6 plus O2 plus Ar; tune ratio for profile target]
    G --> I[Mask strip: H2SO4 plus H2O2 piranha or selective O2 RIE]
    H --> I
    I --> J[SEM cross-section for profile and sidewall angle]
    J --> K[AFM roughness map: Ra target below 1 nm]
    K --> L{Spec met?}
    L -->|Yes| M[XPS plus SIMS post-etch characterization then device integration]
    L -->|No| E

Post-etch characterization is as demanding as the etch itself because SiC surfaces that look geometrically correct in top-view SEM can harbour fluorine-rich sidewall residue, metallic contamination from mask erosion, and shallow crystal damage that degrades final device performance by mechanisms invisible to optical inspection. XPS depth profiling of etched trench sidewalls and floors resolves the elemental composition of residual SiOFₓ and any C-F polymer that survived the mask-strip step; fluorine atomic concentration in the as-etched condition is compared against NIST reference spectra to confirm it falls within a specification window before the wafer advances to gate-dielectric growth, because trapped fluorine at a subsequent SiO₂/SiC interface raises interface trap density $D_{it}$ and degrades channel mobility in trench MOSFETs. AFM in tapping mode provides Ra surface roughness maps of the trench floor and sidewall; for power trench MOSFET gates, a floor roughness above 1 nm Ra correlates with elevated interface state density at the gate oxide, making AFM a mandatory gate in the process flow rather than an optional audit step. SIMS depth profiling on companion samples etched under the same conditions quantifies metallic contamination introduced by Ni mask sputtering — nickel is a deep-level recombination centre in SiC and its near-surface concentration must be held below a process-specific limit established by device lifetime testing — as well as residual fluorine and oxygen incorporated into the top 50 nm to 100 nm of the SiC crystal during the plasma exposure. Hall effect measurements on van der Pauw structures in the same implanted layer as the active device region confirm that near-surface carrier mobility has not been degraded by ion-bombardment-induced displacement damage, which at 250 V to 300 V bias can extend 30 nm to 50 nm below the nominal etch stop depth. ellipsometry on SiO₂ reference pads located on the wafer periphery measures any oxide thinning caused by the O₂ and F* flux reaching the field regions during the etch, providing an indirect measure of lateral etch-chemistry exposure at mask edges. Reactive-ion-etch lag — the phenomenon by which smaller trench openings etch more slowly than larger open areas under nominally identical plasma conditions — is more severe in SiC than in silicon because the SiOFₓ passivation film that accumulates on sidewalls and etch floors inside narrow features is chemically tougher and requires a higher ion energy to sputter-clear than the analogous polymer films in silicon Bosch processes. Lag factors of 20% to 40% in etch rate between 1 µm-wide and 10 µm-wide trenches have been measured on 4H-SiC in SF₆/O₂/Ar at 2 kW ICP power and 150 V bias, creating a depth non-uniformity that is unacceptable for superjunction SiC power structures where the p- and n-pillar column depth must be uniform to within a few percent across the die. Compensating for lag requires either switching to Bosch-mode cycling, which reduces net etch rate to 150 nm/min to 300 nm/min but greatly improves depth uniformity across feature sizes, or applying bias-assist pulses at 400 kHz superimposed on the DC bias to increase ion directionality inside deep narrow trenches without raising the average ion energy at exposed mask surfaces. The Bosch mode for SiC substitutes a brief O₂-only or reduced-SF₆ passivation phase that deposits SiOFₓ on the trench sidewall, followed by an SF₆/Ar-heavy etch phase that clears the trench floor while the passivation protects the walls; cycle times of 10 s to 30 s (etch) and 5 s to 15 s (passivation) are typical starting points.