Sidewall Image Transfer (SIT) is the self-aligned patterning technique that uses the sidewall spacers deposited on a lithographically defined mandrel as the actual etch mask, enabling feature pitches half of (or less than) the minimum lithography pitch — the core mechanism behind all pitch-halving (SADP) and pitch-quartering (SAQP) multi-patterning schemes used at sub-20nm nodes where features must be patterned finer than the optical lithography resolution limit.

Why SIT Is Needed

• ArF immersion lithography minimum half-pitch: ~38 nm (NA=1.35, λ=193nm).
• 10nm node requires 28nm half-pitch → below direct patterning capability.
• EUV (NA=0.33): ~16 nm half-pitch → sufficient for 5nm but needs help at 3nm.
• Solution: SIT doubles the number of features from a single litho exposure → pitch × 1/2 per application.

SIT / SADP Process Flow (Pitch Halving)

1. Deposit mandrel layer (poly, TEOS, or amorphous Si)
2. Litho: Pattern mandrels at 2× target pitch → develop + etch mandrel
3. Spacer deposition: Conformal ALD oxide or nitride (thickness = target half-pitch)
4. Spacer etchback: Anisotropic RIE → removes horizontal spacer, leaves vertical sidewall spacers
5. Mandrel removal: Selective etch (removes mandrel, leaves spacers intact)
6. Spacers now at target pitch (2× the original feature count)
7. Use spacers as etch mask → transfer pattern into underlying material
8. Strip spacers

Pitch Relationship

• Mandrel pitch = 2 × final target pitch
• Spacer width = final line width = final space width (self-defined by ALD thickness)
• Result: 2 spacer lines per mandrel → 2× feature density from 1 litho exposure

SADP (Self-Aligned Double Patterning)

• Single SIT application → 2× feature count (pitch halving).
• Used for fin patterning (FinFET), gate cut layers, metal layers at 10nm–5nm.
• Critical: Spacer ALD thickness controls CD → ALD uniformity (±0.1 nm) is the CD control lever.

SAQP (Self-Aligned Quadruple Patterning)

• Two sequential SIT steps → 4× feature count (pitch quartering).
• SAQP flow: Litho at 4× pitch → SIT 1 (2× pitch) → SIT 2 (1× pitch).
• Used for contacted poly pitch (CPP) patterning at 7nm–5nm.
• Each SIT step adds process complexity and overlay budget consumption.

Spacer Material Selection

CD Uniformity in SIT

• Line CD: Set by spacer ALD thickness → controlled to ±0.2 nm (ALD is very uniform).
• Space CD: Set by mandrel CD after mandrel etch → controlled by litho + etch → ±1–2 nm.
• Result: Odd-even CD asymmetry (line ≠ space) → must be compensated by spacer thickness or mandrel bias.

SIT Limitations

• Lines always in pairs → any single line or line-end requires a separate etch (block mask or cut mask).
• Cut masks (lithography): Add back design-specific features that SIT cannot create.
• EUV replaces many SIT applications at 3nm → simpler flow, but SIT still used for the finest pitches.

Sidewall image transfer is the patterning workhorse that enabled CMOS scaling from 20nm to 5nm — by exploiting ALD thickness as a precision CD ruler and self-alignment to eliminate overlay errors between mandrel and spacer, SIT consistently delivers sub-10nm features without requiring lithography tools beyond their physical capability, making it indispensable to every advanced node manufactured in the last decade.