SiGe/Germanium Channel is the use of silicon-germanium alloy or pure germanium as the transistor channel material to boost hole mobility for PMOS devices — providing 2-4x mobility enhancement over silicon through biaxial or uniaxial compressive strain, enabling balanced NMOS/PMOS performance in advanced CMOS logic.

Why SiGe/Ge for PMOS?

• Silicon has inherently lower hole mobility (~200 cm²/V·s) than electron mobility (~500 cm²/V·s).
• This NMOS/PMOS asymmetry means PMOS transistors must be ~2x wider to match NMOS current — wasting area.
• Germanium: Hole mobility ~1900 cm²/V·s (nearly 10x silicon).
• SiGe (Si0.5Ge0.5): Hole mobility ~500-800 cm²/V·s under compressive strain.

Strain Engineering with SiGe

• Uniaxial Compressive Strain: Embedded SiGe (eSiGe) in source/drain regions compresses the Si channel.
• Introduced by Intel at 90nm (2003) — 25% PMOS drive current improvement.
• SiGe has larger lattice constant than Si → embedded SiGe pushes channel atoms together → compressive strain → enhanced hole mobility.
• Channel SiGe: Replace Si channel entirely with SiGe alloy.
• Higher Ge content → higher mobility but more defects.
• Typical: Si0.7Ge0.3 to Si0.5Ge0.5 for 50-100% mobility boost.

SiGe/Ge Channel in Advanced Nodes

• FinFET: SiGe fins for PMOS (Intel 10nm, TSMC 5nm use SiGe in PMOS S/D; some use SiGe channel).
• Nanosheet/GAA: SiGe channels planned for PMOS nanosheets at sub-2nm nodes.
• Complementary FET (CFET): NMOS Si nanosheets stacked above PMOS SiGe nanosheets.

Germanium Channel Challenges

Roadmap

• Current production: SiGe S/D epitaxy (compressive strain) — universal at 14nm and below.
• Near-term: SiGe channel nanosheets for PMOS (2nm-equivalent node).
• Long-term: Pure Ge PMOS + Si or III-V NMOS in CFET configuration.

SiGe/Ge channel technology is the primary mobility enhancement strategy for PMOS transistors — evolving from embedded source/drain stressors to full channel replacement as the industry requires ever-higher hole mobility at each successive technology node.