A silicon-germanium heterojunction bipolar transistor is a vertical NPN device whose epitaxial base changes band structure and doping. Fabrication must grow a low-defect SiGe:C base, place boron, form a shallow emitter junction, balance collector resistance and capacitance, and share a thermal history with CMOS. Release depends on distributions of gain, breakdown, speed, noise, and matching—not one attractive profile.

Read SiGe HBT fabrication through a bandgap-engineered-base lens rather than a plain-silicon-bipolar lens. Germanium lowers the base bandgap and can be graded through the base to establish a built-in field that assists electron transport. That permits a highly doped, very thin base without paying the same emitter-injection penalty as a silicon homojunction transistor. Carbon is not the speed mechanism; it is a profile-retention tool that suppresses boron diffusion during later thermal cycles. The resulting fT, fmax, gain, and breakdown emerge from the coupled Ge, B, C, collector, emitter, and extrinsic-resistance budgets.

The collector is designed before the fast base is grown. A low-resistance n+ subcollector connects the active device to its collector contact, while a more lightly doped epitaxial collector supports voltage and limits collector-base capacitance. A selectively implanted collector can raise doping under the intrinsic transistor without loading the entire collector-base junction. Too little charge raises series resistance and encourages high-injection delay; too much charge increases capacitance and electric field, reducing voltage margin. An illustrative stack might use 300 nm of collector epi above the subcollector and target 2 V, 3 V, and 5 V device options through different collector designs rather than one universal profile.

The pre-epitaxy surface determines whether the base starts crystalline. Native oxide, carbonaceous residue, fluorine, and STI-edge polymer can nucleate defects or destroy selectivity. XPS on qualified witnesses can track surface composition, and AFM can screen an illustrative 0.3 nm roughness target over a 5 µm field before growth. A dilute clean that removes 1 nm more silicon than expected can change collector geometry at a shallow junction. Queue time between clean and reduced-pressure CVD therefore belongs in the recipe, along with chamber seasoning and the pattern-density split used to qualify loading.

The base stack is a sequence rather than a uniform alloy. A silicon buffer establishes the lower interface; graded SiGe carries in-situ boron; a silicon cap supports emitter formation. One example uses a 30 nm structural base with germanium rising from 20% toward 30% and a narrower electrical boron width. Strain, segregation, temperature, chemistry, and pattern loading determine the incorporated profile.

Germanium grading changes transport but does not erase junction physics. The reduced base bandgap improves electron injection relative to reverse hole injection, raising useful current gain at a given base resistance. A Ge gradient can create a quasi-electric field that shortens base transit time, but an abrupt composition error can introduce barriers or local strain relaxation. Raising peak Ge from 20% to 30% may improve the intended bandgap profile while tightening critical-thickness and defect margins. Gain must therefore be read with base current, ideality, temperature, and collector bias; a single beta value cannot prove the Ge profile is correct.

SIMS supplies central depth evidence for Ge, B, and C, but matrix effects and resolution matter for a base only tens of nm thick. A measured 35 nm boron feature may represent a 30 nm feature broadened by 5 nm of response. Report sputter conditions and depth calibration. XPS supports interface chemistry, ellipsometry tracks identifiable thickness, and cross-sections anchor layer placement.

Carbon protects the boron profile only inside a qualified window. A representative SiGe:C base might contain 0.2% carbon to reduce transient-enhanced boron diffusion. Insufficient carbon provides little protection during a 1000°C CMOS anneal; excess or poorly placed carbon can create defects, compensate strain behavior, or degrade transport. Carbon should overlap the region whose boron profile must remain abrupt without extending casually into interfaces. A thermal split comparing 900°C, 950°C, and 1000°C exposures can reveal whether the 30 nm electrical base broadens beyond its allowed range.

The emitter module converts the epitaxial cap into a controlled emitter-base junction. A dielectric stack defines an emitter opening, a self-aligned spacer limits overlap, and in-situ doped or implanted polysilicon supplies emitter dopant. Dopant out-diffusion into the cap forms the junction, so anneal time shifts electrical base width even if the as-grown SiGe profile is unchanged. An illustrative 120 nm emitter width with 20 nm spacer variation can materially change emitter resistance and overlap capacitance. CD, spacer, cap thickness, and emitter sheet resistance must therefore be released together.

The extrinsic base determines whether intrinsic speed survives layout. The intrinsic base beneath the emitter may be exceptionally fast, yet current still crosses an extrinsic base region, silicide, contact, and metal. Higher base doping and a raised extrinsic base reduce resistance, but can increase junction area or complicate selective growth. four-point probe monitors on appropriate films and Kelvin structures can separate sheet from contact contributions. If base resistance rises 15% while the intrinsic fT proxy is stable, fmax can degrade even though the vertical transit profile has not changed.

Transit frequency and maximum oscillation frequency answer different questions. fT is obtained from short-circuit current gain after pad and interconnect de-embedding; it reflects emitter charging, base transit, collector depletion transit, and high-injection effects. fmax additionally penalizes base resistance, collector-base capacitance, and output conductance. An illustrative total delay of 0.00053 ns corresponds to about 300000 MHz through fT = 1/(2 pi tau). A published device may demonstrate 300000 MHz fT and 420000 MHz fmax, but those peaks are geometry-, current-, and extraction-specific rather than process guarantees.

Keysight network analyzers acquire S-parameters; open, short, and through structures support de-embedding. Report span, bias, geometry, correction method, gain metric, and extrapolation interval. A smooth 20 dB-per-decade fit does not excuse pad coupling. Keithley instruments can collect Gummel, output, leakage, and breakdown curves at the same site.

DC evidence protects the RF interpretation. A Gummel plot separates collector and base current, exposes recombination, and yields gain versus current density. BVCEO couples collector-base avalanche with transistor feedback, so higher gain can reduce common-emitter breakdown. Illustrative gates might hold gain within 10%, check leakage at 1 V, and require BVCEO above 1.8 V for one option or 3.3 V for another.

BiCMOS integration is ultimately a thermal-budget negotiation. CMOS source-drain activation, silicide, contact formation, and dielectric cures can move boron or alter resistance after the HBT base is grown. Millisecond-scale annealing, lower-temperature silicide, and lower-temperature contacts can protect the narrow profile, but every alternative needs its own defect, resistance, and reliability evidence. A 50°C reduction in one module may preserve the base yet increase contact resistance; a 10 s shortened anneal may change CMOS activation. Integration succeeds when both device families meet specifications on the same thermal history.

BiCMOS architecture and HBT option targets
  -> Form n+ subcollector and collector epitaxy
  -> Define shallow trench isolation and collector reach-through
  -> Clean active silicon and qualify selective-growth surface
  -> Grow Si buffer, graded SiGe:C base, boron profile, and Si cap
  -> Measure Ge, B, C depth profiles and epi morphology
  -> Pattern intrinsic and raised extrinsic base regions
  -> Define emitter opening, spacers, and polysilicon emitter
  -> Apply guarded junction-forming and CMOS thermal cycles
  -> Form base, emitter, collector silicide and contacts
  -> Complete shared interconnect without exceeding thermal limits
  -> Measure Gummel, leakage, gain, BVCEO, sheet and contact resistance
  -> De-embed RF structures and extract fT, fmax, Ccb, and Rb
  -> Correlate profile, parasitic, DC, RF, and reliability distributions
  -> Release only when HBT and CMOS process windows overlap

Manufacturing release closes profiles, parasitics, and reliability together. The golden path is a calibrated collector, defect-free epitaxy, intentionally graded Ge, thermally retained boron, correctly placed carbon, a self-aligned emitter, low extrinsic resistance, controlled Ccb, and defensible DC/RF extraction. Failure analysis should trace a low-fT excursion through current density and profile evidence, and a low-fmax excursion through base resistance and capacitance before changing the epitaxy. That bandgap-engineered-base lens preserves the central advantage of SiGe while making clear that BiCMOS performance is created by the whole integration sequence.