Sigma-Delta ADC Architecture is the oversampling analog-to-digital conversion approach that trades conversion speed for resolution by sampling the input signal at many times the Nyquist rate and using a noise-shaping feedback loop to push quantization noise energy away from the signal band, followed by a digital decimation filter that extracts the high-resolution output — achieving 16-24 bit resolution for applications including audio, precision measurement, and sensor interfaces.

Operating Principle:

• Oversampling: the modulator samples the input at a rate (fs) much higher than twice the signal bandwidth (f_BW), typically 64-256 times (oversampling ratio, OSR); each doubling of OSR improves SNR by 3 dB for a first-order modulator (equivalent to 0.5 bits of resolution)
• Noise Shaping: the feedback loop applies a high-pass transfer function to quantization noise while maintaining a flat (unity) transfer function for the input signal; quantization noise energy is pushed to higher frequencies outside the signal band where it is subsequently removed by the decimation filter
• 1-Bit Quantizer: the simplest modulator uses a single comparator as a 1-bit quantizer, producing a dense bitstream of +1/-1 decisions; despite extreme quantization, the noise-shaping feedback ensures that the in-band noise is far below 1-bit levels after decimation
• Multi-Bit Quantizers: using 3-5 bit internal quantizers reduces the quantization noise power before shaping, enabling lower OSR for the same resolution; however, multi-bit DAC linearity in the feedback path must match the target resolution, requiring dynamic element matching (DEM) or calibration

Modulator Architecture:

• First-Order Modulator: single integrator with negative feedback; provides 9 dB/octave noise shaping; limited to approximately 12-bit resolution at practical OSRs; used in simple sensor interfaces
• Second-Order Modulator: two cascaded integrators provide 15 dB/octave noise shaping; achieves 16-18 bit resolution at OSR of 128-256; the standard topology for audio ADCs
• Higher-Order Modulators: third-order and above provide progressively steeper noise shaping but risk instability; stability is ensured through careful coefficient design, multi-bit quantization, or cascaded (MASH) architectures that combine multiple lower-order stages
• Continuous-Time vs. Discrete-Time: discrete-time modulators use switched-capacitor circuits sampled at fs; continuous-time modulators use active-RC or Gm-C integrators with inherent anti-aliasing, enabling higher sampling rates with lower power consumption

Decimation Filter:

• Sinc Filter: the first decimation stage uses a cascaded integrator-comb (CIC or sinc) filter that efficiently removes out-of-band noise and reduces the data rate; sinc³ or sinc⁴ filters provide adequate stopband rejection for most applications with simple hardware implementation
• FIR Compensation Filter: a downstream FIR filter compensates for the sinc filter's droop in the passband and provides a sharp transition band; the combined sinc+FIR chain achieves the target signal bandwidth with flat passband and adequate stopband rejection
• Output Data Rate: the final output rate equals fs/OSR, matching the Nyquist rate for the signal bandwidth; higher OSR provides higher resolution but lower output data rate for a given clock frequency

Performance Metrics:

• SNR and ENOB: signal-to-noise ratio determines the effective number of bits (ENOB = (SNR - 1.76)/6.02); state-of-the-art sigma-delta ADCs achieve ENOB of 20-24 bits for audio bandwidths and 14-18 bits for MHz-range bandwidths
• Power Efficiency: measured by the Walden FOM (energy per conversion = Power/(2^ENOB × BW)); continuous-time modulators achieve FOM values below 10 fJ/conversion-step for high-resolution applications

Sigma-delta ADC architecture is the enabling conversion technology for applications demanding the highest resolution — providing 20+ effective bits through the elegant combination of oversampling, noise shaping, and digital filtering that transforms coarse analog quantization into precise digital representation.