Signal Integrity (SI) Analysis is the comprehensive evaluation of electrical signal quality on chip interconnects, detecting and quantifying crosstalk noise, IR drop shifts, simultaneous switching noise, ringing, and electromigration — ensuring every signal arrives with sufficient noise margin and correct timing.

Crosstalk: Dominant SI concern. As pitch shrinks, coupling capacitance between adjacent wires exceeds substrate capacitance. Two effects:

• Crosstalk delay: Aggressor switching same direction speeds victim; opposite direction slows it. Can add 15-30% timing variation. SI-aware STA models worst-case delta delay.
• Crosstalk glitch: Aggressor injects voltage bump on quiet victim. If amplitude exceeds noise immunity (~30-40% VDD), it propagates through logic and gets captured by a FF.

SI Analysis Flow:

Aggressor Filtering: For billions of nets, tools use: coupling threshold, timing window overlap, logical correlation (same-clock nets excluded from worst case), and spatial proximity.

Prevention Techniques: Shielding (grounded tracks between sensitive signals); spacing via NDR rules; wire sizing (wider victim reduces coupling ratio); buffer insertion (shorter segments); net ordering (co-switching nets adjacent).

Advanced Challenges: BEOL scaling increases resistance (thin Cu/Co/Ru) and coupling (denser pitch). BSPDN frees front-side metals for better SI.

SI analysis has evolved from post-route check to design-through-signoff discipline — SI effects account for 20-30% of total path delay at advanced nodes.