Silicide Formation is the self-aligned metallization process that creates a low-resistance metal-silicon compound (NiSi, NiPtSi, TiSi2, or CoSi2) on the exposed silicon surfaces of the source, drain, and polysilicon gate — providing the critical low-resistance interface between the silicon device and the metal contact plug, without which contact resistance would dominate total device resistance at advanced nodes.
Why Silicides Are Necessary
Silicon, even when heavily doped (>10²⁰/cm³), has sheet resistance of 50-200 Ohm/sq — far too high for low-resistance connections. Silicides provide sheet resistance of 5-10 Ohm/sq and, more critically, form a low Schottky-barrier contact to the underlying doped silicon, reducing the specific contact resistivity to ~10⁻⁸-10⁻⁹ Ohm·cm².
The SALICIDE (Self-Aligned Silicide) Process
1. Pre-Clean: Native oxide on exposed silicon surfaces is removed by dilute HF or vapor-phase cleaning. Any residual oxide between the metal and silicon prevents silicide reaction.
2. Metal Deposition: A thin Ni (or NiPt alloy, 5-15 nm) film is deposited by PVD (sputtering) over the entire wafer — covering silicon (S/D, gate), oxide (STI, spacers), and nitride (spacers) surfaces.
3. First Anneal (RTA, 250-350°C): Nickel reacts with silicon where it contacts exposed silicon, forming Ni2Si (metal-rich phase). On oxide and nitride surfaces, no reaction occurs — the metal remains unreacted.
4. Selective Etch: Unreacted Ni on oxide/nitride surfaces is removed by a selective wet etch (SPM: sulfuric-peroxide mixture). Ni2Si on silicon is not attacked. This is the "self-aligned" step — no lithography is needed to define the silicide regions.
5. Second Anneal (RTA, 400-500°C): Ni2Si transforms to the desired low-resistivity NiSi phase. Controlled temperature prevents further transformation to the high-resistivity NiSi2 phase.
Silicide Material Evolution
| Generation | Material | Nodes | Sheet Resistance | Challenge |
|-----------|---------|-------|-----------------|----------|
| 1st | TiSi2 | >250nm | 5-8 Ohm/sq | Line-width effect |
| 2nd | CoSi2 | 180-90nm | 5-7 Ohm/sq | High Si consumption |
| 3rd | NiSi | 65-14nm | 5-10 Ohm/sq | Thermal stability |
| 3rd+ | NiPtSi | 45-7nm | 6-12 Ohm/sq | Improved agglomeration resistance |
Advanced Node Challenges
- Agglomeration: At elevated temperatures (>500°C), NiSi films break apart into discrete islands, destroying the continuous low-resistance layer. Adding 5-10% Pt to the Ni suppresses agglomeration by ~100°C.
- Silicon Consumption: Each nm of Ni consumes ~1.8 nm of Si during reaction. In shallow junctions (<10 nm) and thin fins, excessive Si consumption can punch through the junction, creating leakage. Ultra-thin Ni films (<5 nm) are needed at 7nm and below.
- FinFET/GAA: Silicide forms on the exposed epitaxial S/D facets. The 3D geometry and SiGe S/D composition add complexity — germanosilicide (NiSiGe) has different formation kinetics and resistivity.
Silicide Formation is the chemical handshake between the silicon transistor world and the metal interconnect world — creating the low-resistance bridge that carries current from the channel into the wiring network above.