Silicon controlled rectifier (SCR) for ESD is the highest current-density ESD protection device available in CMOS technology, using a four-layer PNPN thyristor structure — capable of conducting the most ESD current per unit area of any clamp type due to its deep snapback to very low holding voltage, but requiring careful design to prevent latchup.

What Is SCR for ESD?

• Definition: A PNPN (thyristor) device structure formed in CMOS technology that provides ESD protection through regenerative feedback between cross-coupled PNP and NPN bipolar transistors.
• Four Layers: P+ anode → N-well → P-substrate → N+ cathode form the PNPN stack.
• Deep Snapback: When triggered, the SCR's voltage drops to approximately 1.2-2.0V (one PN junction forward drop) while conducting multi-ampere currents.
• Highest Efficiency: SCR provides 10-20 mA/µm current handling — 2-4× more than GGNMOS — making it the smallest ESD clamp for a given protection level.

Why SCR ESD Clamps Matter

• Area Efficiency: For area-constrained designs (mobile SoCs, IoT chips), SCR-based protection achieves the required ESD withstand voltage in the smallest possible silicon area.
• High Current Capacity: The regenerative PNPN action provides extremely low on-resistance, enabling very high ESD current handling.
• Low Clamping Voltage: Deep snapback to ~1.5V means minimal voltage across the clamp during an ESD event, reducing stress on interconnects.
• Advanced Node Necessity: At 5nm and below, available layout area for ESD devices shrinks dramatically — SCR's superior area efficiency becomes essential.
• Automotive Applications: High-voltage automotive I/O (12V, 24V, 48V) benefits from SCR's ability to handle large ESD currents in high-voltage designs.

SCR Operation Mechanism

Phase 1 — Off State:

• Both PNP and NPN transistors are off.
• Only junction leakage flows (pA range).

Phase 2 — Trigger:

• External trigger (avalanche, diode chain, or GGNMOS-assisted) injects current into the base of either the PNP or NPN transistor.
• This is the most critical design challenge — native SCR trigger voltage is often 15-25V, too high for direct ESD protection.

Phase 3 — Regenerative Turn-On:

• PNP collector current feeds into NPN base.
• NPN collector current feeds back into PNP base.
• Positive feedback causes rapid regenerative turn-on — both transistors saturate.

Phase 4 — Sustained Conduction:

• Device operates at Vh ≈ 1.2-2.0V with very low impedance.
• Current flows through the entire PNPN structure with uniform distribution.

SCR Design Challenges

SCR Design Variants

• LVTSCR (Low-Voltage Trigger SCR): Integrates a short-channel NMOS to reduce trigger voltage to 6-8V using avalanche-assisted triggering.
• DTSCR (Diode-Triggered SCR): Uses a diode string to trigger the SCR at a controlled voltage defined by the number of stacked diodes.
• MLSCR (Modified Lateral SCR): Adds N+ and P+ diffusions to control the current gain and holding voltage of the parasitic bipolar transistors.
• Segmented SCR: Breaks the SCR into smaller cells with added resistance between segments to raise the effective holding voltage above VDD.
• Stacked SCR: Series-connected SCR cells for high-VDD applications where a single SCR's Vh is too low.

When to Use SCR vs. GGNMOS

SCR for ESD is the nuclear option in the ESD designer's arsenal — delivering unmatched current density and area efficiency at the cost of increased design complexity, making it the protection device of choice when every square micron counts.