CoWoS (Chip on Wafer on Substrate) is TSMC's 2.5D advanced packaging platform using silicon interposer, RDL layers, and chiplet integration to achieve high-bandwidth memory (HBM) and logic aggregation.
CoWoS Family of Products:
- CoWoS-S (standard): silicon interposer routing, HBM2/HBM3 integration
- CoWoS-L (local): increased local silicon functionality (limited processing)
- CoWoS-R (RDL): passive silicon interposer (no active devices)
- CoWoS Evolution: first shipped ~2013 (Nvidia Kepler), continuously upgraded
Silicon Interposer Design:
- Passive interposer: silicon die containing only wiring (RDL + TSVs)
- No logic: reduces power dissipation vs active interposer approach
- Wiring efficiency: short direct paths from logic die to HBM
- TSV density: enables fine-pitch interconnect (pitch 40-50 µm typical)
HBM Integration in CoWoS:
- HBM stacking: 2-4 HBM stacks beside single logic die
- Bandwidth advantage: >500 GB/s vs external DRAM (<100 GB/s)
- Physical proximity: HBM at same package level (minimal latency, inductance)
- Cost: HBM expensive, only justified for bandwidth-critical (GPU, AI training)
2.5D vs 3D Packaging Comparison:
- 2.5D (CoWoS): dies on same package-substrate level, interposer routes signals
- 3D (chiplet stacking): dies stacked vertically, TSV through-silicon vias
- 2.5D advantage: mature, lower thermal challenges, chiplet independence
- 3D advantage: smaller footprint, higher density
RDL (Redistribution Layer) in CoWoS:
- RDL routing: multiple metal layers on silicon interposer surface
- Fine-pitch capability: enables routing all signals between dies
- Layer count: 3-5 RDL layers typical, routing density optimization
- Dielectric material: polyimide or PBO (low-Dk ~3)
Power Distribution Challenge:
- Power delivery network (PDN): HBM and logic have different supply requirements
- Decoupling capacitors: on interposer or substrate
- Ground vias: coarse grid for return path, minimize loop inductance
- IR drop: optimize power pin distribution (bottleneck for high-current HBM)
Thermal Management:
- Heat dissipation: logic die generates heat (GPU >200W typical)
- Substrate thermal path: copper layers transfer heat downward
- Underfill material: low thermal conductivity (vs thermal fillers being developed)
- Temperature gradient: interposer may be hottest due to die-substrate interface
Manufacturing and Yield:
- Cost per unit: moderate (cheaper than 3D chiplet stacking)
- Process maturity: TSMC CoWoS experienced, multiple-generation shipping
- Substrate warp: large interposer substrates prone to warping
- Known-good-die (KGD): testing logic/HBM before assembly critical
CoWoS established 2.5D as mainstream for next-decade heterogeneous computing—competing with chiplet I/O density targets but proven reliability advantage.