Silicon crystal orientations refer to the specific crystallographic planes used as the surface of silicon wafers — identified by Miller indices like (100), (110), and (111), each orientation provides different electrical, chemical, and mechanical properties that affect transistor performance, etching behavior, and process compatibility.

What Are Silicon Orientations?

• Definition: Crystallographic planes exposed at the wafer surface.
• Notation: Miller indices (hkl) specify the plane orientation.
• Common Types: (100), (110), and (111) for silicon.
• Identification: Notch or flat position indicates orientation.

Why Orientation Matters

• Device Performance: Carrier mobility varies with orientation.
• Etch Behavior: Wet etch rates differ 10-100× by plane.
• Oxidation Rates: (111) oxidizes faster than (100).
• Manufacturing Compatibility: Most CMOS uses (100).
• MEMS Applications: (110) and (111) for specific structures.

Silicon Crystal Structure

Silicon has a diamond cubic crystal structure:

• Face-centered cubic with 2-atom basis.
• Lattice constant: 5.431 Å at room temperature.
• Each atom bonded to 4 neighbors tetrahedrally.

Major Orientations

(100) Orientation:

• Usage: Standard for CMOS manufacturing (>95% of wafers).
• Properties: Good oxide interface quality, lowest surface state density.
• Mobility: Moderate electron mobility, enhanced by strain.
• Etch: KOH etches to form angled (111) sidewalls.

(110) Orientation:

• Usage: Some MEMS devices, niche applications.
• Properties: Higher hole mobility than (100).
• Etch: Vertical sidewalls in certain etch directions.
• Challenge: More difficult to process, less common infrastructure.

(111) Orientation:

• Usage: Bipolar transistors, some specialty devices.
• Properties: Highest atomic density, slowest etch plane.
• Etch: Serves as etch stop in anisotropic etching.
• History: Originally common, now mostly for specific applications.

Orientation Impact on Properties

Carrier Mobility:

Orientation | Electron µ | Hole µ   | Preferred
------------|------------|----------|------------
(100)       | 1350       | 450      | Standard CMOS
(110)       | 900        | 600      | pFET on strained
(111)       | 900        | 400      | Bipolar, legacy
Units: cm²/V·s at 300K, unstrained silicon

Oxide Quality:

• (100): Lowest interface trap density (Dit ~ 10¹⁰/cm²·eV).
• (111): Higher interface traps, more challenging oxidation.
• (110): Intermediate quality.

Wet Etch Rates (KOH):

• (100): Fast etching (1-2 µm/min).
• (110): Medium etching.
• (111): Very slow (etch stop plane, ~30× slower than 100).

Wafer Identification

Flat/Notch Position:

(100) n-type: Primary flat on (011)
(100) p-type: Primary flat on (011), secondary flat 180° opposite
(111) n-type: Primary flat on (011)
(111) p-type: Primary flat on (011), secondary flat 45° offset

Modern Wafers:

• 200mm: Use flats for orientation identification.
• 300mm: Use single notch (standard position varies by spec).

Applications by Orientation

• (100): CMOS, memories, most digital ICs.
• (110): Advanced pFETs, some MEMS actuators.
• (111): MEMS structures (etch stop), bipolar transistors, LEDs.

Silicon orientation is a foundational choice in semiconductor manufacturing — the crystallographic plane at the wafer surface determines carrier mobility, oxide quality, etch behavior, and process compatibility, making (100) the dominant choice for modern CMOS while other orientations serve specialized applications.