Semiconductor Materials Characterization: SIMS, XPS, and TEM is the suite of analytical techniques used to measure the chemical composition, elemental depth profiles, bonding states, and atomic-scale structure of semiconductor materials and thin films — providing the ground truth measurements that verify process completion, validate new materials, diagnose process failures, and ensure that device physics requirements (e.g., junction depth, gate dielectric composition, interface quality) are met with angstrom-level precision.
SIMS (Secondary Ion Mass Spectrometry)
- Primary ion beam (Cs+, O₂+) sputters surface → secondary ions ejected → mass spectrometer measures composition.
- Measures: Depth profiles of dopants (B, P, As, In), trace impurities, isotope ratios.
- Depth resolution: 1–5 nm.
- Detection limit: 10¹⁴–10¹⁵ atoms/cm³ (ppb level) → detects trace contamination invisible to other techniques.
- Dynamic SIMS: Fast sputtering → depth profile analysis (sacrifices mass resolution for speed).
- Static SIMS: Very slow sputtering → surface analysis of monolayers (ToF-SIMS).
Key SIMS Applications
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Boron junction in silicon:
Concentration (atoms/cm³)
10²¹ |████
10²⁰ | ████
10¹⁹ | ████
10¹⁸ | ████
10¹⁷ | ████ ← junction depth (Xj)
10¹⁶ | background
0 10 20 30 40 nm depth
SIMS measures Xj to ±1 nm accuracy
- Gate oxide nitrogen profile: N₂ plasma nitridation → SIMS confirms N at SiO₂/Si interface.
- High-k/metal gate stack: HfO₂ composition, La₂O₃ doping concentration → verify EOT control.
- Carbon in SiGe channel: C incorporation affects strain → SIMS quantifies C at 0.1–2% levels.
XPS (X-ray Photoelectron Spectroscopy)
- X-ray illumination → photoelectrons emitted → kinetic energy → binding energy → element + bonding state.
- Surface sensitive: ~5–10 nm sampling depth → ideal for thin films and interface analysis.
- Measures: Chemical bonding states (Si⁰, Si⁴⁺, Si^(2+)), not just elemental composition.
- Depth profiling: Angle-resolved XPS (ARXPS) → non-destructive; Ar+ sputter + XPS → destructive.
XPS Bonding State Analysis
- Si 2p spectrum: Si metal (99.3 eV) vs SiO₂ (103.3 eV) → oxide thickness from area ratio.
- HfO₂/SiO₂/Si stack: Multiple Si oxidation states → deconvolute → interfacial layer thickness.
- Metal gate: TiN bonding states → N:Ti ratio, oxygen contamination → verify gate stack quality.
- ALD precursor residue: Carbon contamination from TMA (trimethylaluminum) → verify clean ALD Al₂O₃.
TEM (Transmission Electron Microscopy)
- High-energy electron beam through ultra-thin sample (< 100 nm) → image atomic structure.
- HRTEM: Atomic column resolution < 1 Å → image crystal structure, interface abruptness.
- STEM-HAADF: Z-contrast imaging → heavy atoms appear bright → measure composition spatially.
- EELS (Electron Energy Loss Spectroscopy): Chemical bonding in TEM → element maps.
- Sample prep: FIB cross-section → lamella thinning to 50–100 nm → carbon/Pt protective coating.
TEM Applications in Semiconductor
- Gate oxide integrity: Image SiO₂/Si interface → confirm interface roughness < 2 Å RMS.
- Nanosheet geometry: Measure sheet thickness (3–5 nm), space between sheets (7–10 nm) → verify GAA process.
- Silicide phase: TiSi₂ C49 vs C54 phase → affects resistance → TEM + diffraction confirms phase.
- Defects: Dislocation loops from implant → TEM quantifies density and size.
Complementary Technique Summary
| Technique | Depth Resolution | Element Range | Bonding Info | Detection Limit |
|-----------|-----------------|--------------|-------------|----------------|
| SIMS | 1–5 nm | All elements | No | 10¹⁴/cm³ |
| XPS | 5–10 nm | All except H,He | Yes | 0.1–1 at% |
| TEM/EELS | < 0.1 nm | Z > 3 | Yes | 1–10 at% |
| RBS | 5–10 nm | Z > 4 | No | 0.1–1 at% |
| EDX (SEM) | 1–2 µm | Z > 4 | No | 0.1–1 wt% |
SIMS, XPS, and TEM characterization are the truth measurement infrastructure of semiconductor process development — without SIMS to confirm that boron junction depths are within 1nm of target, XPS to verify that gate dielectrics are stoichiometric with correct interfacial bonding, and TEM to image that gate oxide/channel interfaces are atomically sharp, process engineers would be optimizing blindly in parameter space, making these analytical techniques the essential feedback loop that connects theoretical process recipes to the atomic-scale physical reality that determines transistor performance and reliability.