Computational Lithography is the use of advanced simulation, optimization, and machine learning algorithms to design photomask patterns and illumination conditions that produce the desired circuit features on the wafer — compensating for the fundamental optical limitations of projecting sub-wavelength features (3-7 nm features using 13.5 nm EUV light) through inverse optimization that makes the mask pattern look nothing like the desired wafer pattern, with computational lithography consuming more compute than any other EDA step.

Why Computational Lithography Is Needed

Desired wafer pattern:    What mask must look like (with OPC):
  ┌──────┐                    ╔══╗
  │      │                   ╔╝  ╚╗
  │      │                   ║    ║  ← Serif, jog corrections
  │      │  ───────→         ║    ║
  │      │  Inverse          ╚╗  ╔╝
  └──────┘  optimization      ╚══╝

Simple rectangle on wafer → complex shape on mask
Because: Light diffracts, interferes, and is collected by finite lens aperture

Computational Lithography Methods

OPC (Optical Proximity Correction)

• Rule-based: Add fixed serifs to corners, bias line widths by space → fast but limited.
• Model-based: Simulate aerial image → iteratively adjust mask edges until wafer image matches target → standard production method.
• Iterations: 10-50 iterations per feature → billions of feature corrections per chip layer.

Inverse Lithography Technology (ILT)

Forward problem: Given mask M → simulate wafer image I(M)
Inverse problem: Given desired wafer target T → find mask M* such that I(M*) ≈ T

Optimization:
  M* = argmin_M || I(M) - T ||² + regularization

Result: Free-form mask patterns (curvilinear, not Manhattan geometry)
  → Better fidelity but much more complex masks

• ILT produces curvilinear mask shapes → requires multi-beam mask writers (variable-shaped beam → too slow).
• Curvilinear masks: 10-30% improvement in pattern fidelity and process window.

Source-Mask Optimization (SMO)

• Optimize both the illumination source shape AND the mask pattern simultaneously.
• Source: Shape of light in the pupil plane (can be freeform, not just standard dipole/quadrupole).
• Joint optimization: Even better results than OPC or ILT alone.

Machine Learning in Computational Lithography

Compute Requirements

• Single EUV layer of an advanced SoC: ~50-100 billion features to correct.
• Model-based OPC: 10,000+ CPU-hours per layer.
• ILT: 100,000+ CPU-hours per layer.
• Full chip, all layers: Millions of CPU-hours → massive GPU/cloud compute.
• Cost: $1-10M in compute per tapeout for computational lithography.

Computational lithography is the mathematical engine that makes sub-wavelength semiconductor manufacturing possible — without the billions of corrections computed by OPC and ILT algorithms, the features printed on modern chips would be unrecognizable blobs rather than the precisely defined transistors and wires that digital civilization depends on, making computational lithography one of the most compute-intensive and commercially critical applications of optimization and machine learning.