Soft IP is a reusable design block delivered as synthesizable RTL source code (Verilog, SystemVerilog, or VHDL) that can be compiled, synthesized, and implemented on any target process technology.

Soft IP vs. Hard IP

• Soft IP: RTL source code. Process-independent. Customer synthesizes to target node. Flexible and portable • Hard IP: Fixed physical layout. Optimized for one specific process. Better PPA (performance, power, area) but not portable

Common Soft IP Blocks

• Processor cores: ARM Cortex-A/M/R series, RISC-V cores. The largest soft IP market • Bus interconnects: AMBA AXI, AHB, APB on-chip interconnect fabrics • Peripheral controllers: UART, SPI, I2C, USB controller logic, PCIe controller • Security: Crypto engines (AES, SHA, RSA), secure boot, DRM • DSP: FFT, FIR filters, signal processing blocks • AI/ML accelerators: NPU cores, neural network inference engines

Soft IP Advantages

Portability: Same IP works on TSMC 7nm, Samsung 5nm, Intel 18A—just re-synthesize. Customization: Customer can modify parameters (bus width, FIFO depth, feature enables). Verification: IP provider delivers comprehensive testbenches and verification suites. Time-to-market: Using pre-verified IP blocks saves 12-24 months of design time versus designing from scratch.

The ARM Business Model

ARM is the most successful soft IP provider. Their processor cores power 99% of smartphones and are expanding into servers and PCs. ARM licenses RTL to customers (Apple, Qualcomm, Samsung) who synthesize the cores into their own chip designs. ARM earns license fees (per design) and royalties (per chip shipped, typically 1-2% of chip ASP).