Selective Epitaxial Growth (SEG) for Source/Drain is the critical front-end process step that grows heavily-doped crystalline semiconductor (Si, SiGe, or SiP) in the source/drain cavities of FinFET and nanosheet transistors — simultaneously providing the electrical contact region for current flow, applying mechanical stress to the channel for mobility enhancement, and minimizing the contact resistance that increasingly dominates total device resistance at advanced nodes.

Why Epitaxial Source/Drain Replaced Ion Implantation

At planar CMOS nodes ≥28nm, source/drain regions were created by implanting dopants into the silicon and annealing to activate them. In FinFETs, the fins are too narrow for reliable implant dose control, and the required doping levels (>1e21/cm³) exceed the solid solubility achievable by implantation. Epitaxial growth with in-situ doping during deposition achieves active doping concentrations 2-5x higher than implantation, directly reducing contact resistance.

PMOS: Embedded SiGe

Epitaxial SiGe (Ge content 30-50%) is grown in etched S/D cavities. Because SiGe has a larger lattice constant than silicon, the epitaxial SiGe compresses the pure-silicon channel, increasing hole mobility by 40-60%. Boron doping exceeding 3e20/cm³ is incorporated in-situ. Diamond-shaped or faceted SiGe profiles maximize the strain transfer and the epitaxial volume for low-resistance contacts.

NMOS: Silicon:Phosphorus (Si:P)

Epitaxial Si:P with phosphorus concentrations up to 3-5e21/cm³ replaces the S/D. The tensile stress from the high phosphorus concentration provides modest NMOS mobility enhancement. More critically, the extreme doping level minimizes the Schottky barrier width at the metal-semiconductor contact, reducing contact resistivity below 1e-9 Ohm-cm².

Process Challenges

• Selectivity: The epitaxy must grow crystalline material only on exposed silicon surfaces, with zero deposition on the surrounding SiN spacers and STI oxide. HCl gas in the precursor mix etches nuclei on dielectric surfaces faster than they form, maintaining selectivity. Loss of selectivity causes polysilicon nodules on the spacer that short the gate to the source/drain.
• Loading Effects: The epitaxial growth rate and composition depend on the local exposed silicon area. Isolated transistors with large exposed S/D areas grow faster than dense arrays. Inter-die and intra-die loading compensation requires careful gas flow and temperature profiling.
• Faceting and Merging: Adjacent fins must grow S/D epi that merges into a continuous contact region, but uncontrolled faceting can create voids at the merge interface that increase resistance.

Selective Epitaxial Growth for Source/Drain is the process that builds the transistor's electrical on-ramp and off-ramp — and at advanced nodes, the quality of this epitaxial contact determines device performance more than the channel itself.