Contact Resistance in Advanced CMOS is the interface resistance between the metal interconnect and the semiconductor source/drain regions — which has become the dominant component of total transistor on-resistance at sub-5nm nodes, now exceeding channel resistance in magnitude, making contact engineering (silicide formation, contact geometry, doping activation) the primary knob for continued transistor performance scaling.
Why Contact Resistance Dominates
Historically, transistor performance was limited by channel resistance (controlled by gate length, mobility, and oxide thickness). As gate lengths shrink below 12nm, channel resistance drops proportionally. Contact resistance, however, is determined by the contact area (which shrinks quadratically with scaling) and the specific contact resistivity (ρc, in Ω·cm²). At 3nm nodes, contact resistance contributes 40-60% of total source-to-drain resistance.
Contact Resistance Physics
R_contact = ρc / A_contact, where ρc depends on the metal-semiconductor barrier height and the semiconductor doping concentration at the interface. The Schottky barrier at the metal-silicon interface creates a resistance that scales exponentially with barrier height. Achieving sub-1×10⁻⁹ Ω·cm² requires:
- Ultra-high surface doping: >1×10²¹ cm⁻³ active dopant concentration at the contact interface to thin the Schottky barrier for efficient quantum tunneling.
- Low barrier height metal: Titanium silicide (TiSi₂) for NMOS, nickel silicide (NiSi) for PMOS traditionally. Research explores alternative contact metals (molybdenum, ruthenium) with lower barrier heights.
Silicide Engineering
Silicide formation (solid-state reaction between deposited metal and silicon) creates the ohmic contact:
- Titanium Silicide (TiSi₂): Re-emerging for advanced nodes due to favorable interface properties. Laser anneal enables ultra-thin (<5nm) silicide with minimal silicon consumption.
- Nickel Silicide (NiSi): Lower formation temperature but prone to agglomeration and NiSi₂ phase transformation at high temperatures. Platinum doping (Ni(Pt)Si) stabilizes the monosilicide phase.
Wrap-Around Contact (WAC)
For gate-all-around nanosheet FETs, the contact must wrap around the stacked nanosheets' source/drain epitaxial regions to maximize contact area. WAC technology:
- Increases effective contact area by 2-3x compared to top-only contact.
- Requires selective etch of the inner spacer material to expose lateral source/drain surfaces.
- Demands conformal silicide formation around 3D topography.
Emerging Solutions
- Semi-Metal Contacts: Bismuth (Bi) and antimony (Sb) semi-metal interlayers eliminate the Schottky barrier entirely by creating a zero-barrier-height interface. Intel demonstrated Bi-based contacts with record-low ρc.
- Dipole Engineering: Inserting thin dielectric dipole layers (TiO₂, LaO) at the metal-semiconductor interface shifts the effective barrier height, reducing contact resistance without changing the contact metal.
Contact Resistance is the scaling bottleneck that has shifted transistor engineering focus from the channel to the source/drain interface — making contact metallurgy, doping, and geometry optimization as critical to performance as gate stack engineering was in the FinFET era.