Source/Drain Epitaxial Growth Selectivity and Faceting Control is the optimization of chemical vapor deposition parameters to achieve perfectly selective single-crystal growth only on exposed silicon or SiGe surfaces while preventing any nucleation on surrounding dielectric materials, with simultaneous control over crystal facet formation that determines contact area geometry and strain transfer efficiency — critical for achieving low parasitic resistance and maximum channel stress in advanced CMOS transistors.

• Selective Epitaxy Mechanism: Selectivity is achieved by balancing deposition and etch reactions; silicon-containing precursors (dichlorosilane, silane, or disilane) deposit on all surfaces, while HCl etchant simultaneously removes nuclei from dielectric surfaces faster than they accumulate, leaving net growth only on the crystalline silicon seed; the selectivity window depends on precursor partial pressures, temperature (typically 550-700 degrees Celsius), and HCl flow rate.
• Loss of Selectivity: If deposition rate exceeds the HCl etch rate on dielectrics, polycrystalline nodules form on oxide and nitride surfaces, potentially causing shorts between adjacent source/drain regions or increasing leakage; selectivity margin is monitored by test structures with varying dielectric-to-silicon area ratios.
• Faceting Origins: Epitaxial growth rates vary with crystallographic orientation, with (100) surfaces growing fastest and (111) surfaces growing slowest; this anisotropy creates faceted profiles with (111) and (311) planes that reduce the effective top surface area available for silicide contact formation.
• Faceting Control Strategies: Cyclic deposition-etch (CDE) processes alternate between non-selective deposition and selective etch steps to periodically remove faceted growth fronts and reset the surface morphology; this approach produces more rectangular profiles with larger flat-top areas compared to continuous selective epitaxy.
• Raised Source/Drain: Growing the epitaxial layer above the original silicon surface (raised S/D) provides additional silicon thickness for silicide consumption, reducing the risk of silicide punch-through to the junction; the raised height is typically 10-25 nm above the adjacent STI oxide surface.
• In-Situ Doping: Boron for PMOS (in SiGe:B) and phosphorus for NMOS (in Si:P) are incorporated during growth at concentrations of 1-5e20 per cubic centimeter; dopant incorporation efficiency depends on growth temperature, rate, and facet orientation, creating non-uniform doping profiles on faceted surfaces that affect contact resistance.
• Loading Effects: The epitaxial growth rate and composition depend on the local ratio of exposed silicon to dielectric area (pattern loading); dense transistor arrays grow differently than isolated devices, requiring compensation through layout-dependent process adjustments or dummy pattern insertion.
• Merging Versus Unmerging: In FinFET architectures, adjacent fin source/drain epitaxial layers can merge into a continuous region or remain as separate pillars depending on fin pitch and growth duration; merged epitaxy provides lower resistance but higher capacitance, while unmerged epitaxy offers the opposite tradeoff. Source/drain epitaxy selectivity and faceting control are fundamental to transistor performance because the source/drain geometry directly determines parasitic resistance, strain magnitude, and contact interface quality in every modern CMOS technology.