Source/Drain Recess Etch and Epitaxial Stressor Integration

Source/Drain Recess Etch and Epitaxial Stressor Integration is the process module that selectively removes silicon from the source and drain regions adjacent to the gate to create cavities — into which strained epitaxial silicon-germanium (for PMOS) or silicon-carbon (for NMOS) is grown, introducing compressive or tensile strain into the transistor channel that increases carrier mobility and drive current without any layout change or voltage scaling, representing one of the most impactful process innovations in the sub-90nm CMOS era.

Why Strained Silicon

- Carrier mobility limited by phonon and impurity scattering in unstrained Si.
- Strain splits degenerate band valleys → reduces intervalley scattering → increases mobility.
- PMOS: Compressive strain → lifts heavy-hole band → light-hole dominant → 50% hole mobility increase.
- NMOS: Tensile strain → splits Δ2/Δ4 valleys → electrons preferentially occupy Δ2 (lighter mass) → 20–30% electron mobility increase.
- Recessed S/D epi: Local strain source → most effective strain delivered to channel → dominates other strain engineering techniques.

Recess Etch Process

- After gate patterning + thin spacer formation → S/D silicon exposed.
- Wet etch: TMAH (tetramethylammonium hydroxide) → anisotropic, {111} faceted etch → ∑-shaped cavity (sigma cavity).
- ∑ profile: Cavity extends partially under gate spacer → positions SiGe stressor closer to channel.
- Etch rate: (100) surface >> (111) surface → facets form naturally.
- Dry etch: Cl₂/HBr → faster, less anisotropic → used when tight process window.

∑ (Sigma) Cavity Shape

``
Before recess: After ∑-etch:
┌──┬─────┬──┐ ┌──┬─────┬──┐
│G │GATE │G │ → │G │GATE │G │
│S │ │S │ │S │ │S │
│p │ │p │ │ \ / │
│ │Si │ │ │ \ ∑ / │
└──┴─────┴──┘ └────V────┘
S/D recess
``

- ∑ cavity extends under gate spacer edge → SiGe fills close to channel → maximum strain.
- Depth control: TMAH time/temperature → typically 30–60 nm deep.

Epitaxial Fill: SiGe for PMOS

- Fill ∑ cavity with Si₁₋ₓGeₓ (x = 25–30%) → compressive strained (Ge lattice larger than Si).
- Ge% determines strain magnitude: 25% Ge → ~1.0% biaxial compressive strain → strong mobility boost.
- In-situ doped: B₂H₆ added → p+ SiGe S/D → low resistance → no separate doping step.
- RPCVD (Reduced Pressure CVD): SiH₂Cl₂ + GeH₄ + B₂H₆ at 650°C → conformal, high-quality SiGe.
- Overfill: SiGe fills cavity + raises above wafer surface → merged SiGe → lower series resistance.

Epitaxial Fill: SiC or Si:P for NMOS

- SiC (Si₁₋yCy, y~1%): Tensile strain (C lattice smaller than Si) → NMOS electron mobility increase.
- C incorporation limited: >2% → misfit dislocations → use SiCP (SiC:P in-situ doped).
- Si:P (phosphorus-doped Si epi): Alternative to SiC; phosphorus provides n+ doping AND slightly tensile strain at high P concentration.
- Modern NMOS (< 16nm): Si:P preferred → SiC strain effect smaller than SiGe for PMOS but still beneficial.

Selective Epitaxy

- Selectivity: SiGe must grow only in Si recess, not on SiO₂ or SiN spacer → HCl etching of mis-nucleated oxide growth → selective process.
- HCl flow rate: Balance deposition (SiH₂Cl₂) vs nucleation removal (HCl) → selective window.
- Nucleation failure: SiGe on spacer → bridges → CD error → process window must be tight.

Source/drain recess and epitaxial stressor integration are the strain engineering revolution that added effectively one generation of CMOS performance without any lithography scaling — by recessing silicon into ∑-shaped cavities and filling with 25% germanium alloy within 10 nm of the channel, Intel's 90nm strained silicon process in 2003 achieved 20–30% drive current increase with no layout change, demonstrating that materials engineering can substitute for the shrinking that lithography technology delivers, a lesson that has been extended to SiGe channels for pFET FinFETs and PMOS nanosheets where the entire channel is now made of high-Ge SiGe alloy for maximum hole mobility.