Spacer Formation — depositing and etching insulating layers on the sidewalls of the gate stack to define the offset between gate edge and deep source/drain implant, a critical dimension control technique.

Purpose

• Defines the lateral distance between gate edge and deep S/D junction
• Protects gate from short-circuiting to S/D during silicide formation
• Enables the LDD/extension architecture (light implant before spacer, heavy implant after)

Process

1. After LDD implant, conformally deposit SiN (or SiO₂ + SiN stack) over entire wafer 2. Anisotropic dry etch (vertical etch rate >> lateral): Removes film from horizontal surfaces, leaves it on vertical sidewalls 3. Result: Uniform spacer width on gate sidewalls (10–30nm)

Spacer Engineering

• Single spacer: One layer (simple, older nodes)
• Dual spacer: Oxide liner + nitride spacer (better control, standard)
• Triple spacer: Used at advanced nodes for multiple implant offsets and self-aligned contact

Multi-Patterning Role

• In SADP (Self-Aligned Double Patterning), spacers ARE the patterning features
• Deposit conformal film → etch → remove mandrel → spacers become the mask
• This is how sub-lithographic features are created

Spacer width directly controls transistor overlap capacitance, series resistance, and short-channel behavior — it's one of the most tightly controlled dimensions in the process.