Spike Anneal is an ultra-short thermal processing technique that reaches peak temperatures above 1000°C with hold times of less than one second, maximizing dopant electrical activation while minimizing diffusion to achieve the ultra-shallow junctions required for sub-65nm transistor fabrication — representing the most thermally aggressive standard RTP process, and the predecessor to flash and laser spike annealing for the most advanced technology nodes below 22nm.

What Is Spike Anneal?

• Definition: An RTP process that ramps rapidly to peak temperature (typically 1000-1100°C on silicon), holds for less than 1 second (the "spike"), then cools rapidly — achieving maximum activation with minimal time-at-temperature and therefore minimal dopant diffusion.
• Zero-Hold Time: The "spike" refers to the instantaneous peak with no intentional dwell — the wafer spends only the thermal ramp time near peak temperature, minimizing the thermal integral.
• Thermal Budget Minimization: By eliminating the hold time present in conventional RTP anneals, spike anneal reduces the thermal integral ∫T(t)dt by 10-100× compared to 10-60 second conventional anneals.
• Activation vs. Diffusion Tradeoff: Activation follows Arrhenius kinetics favoring high temperature; diffusion also follows Arrhenius but with different pre-exponentials — spike anneal exploits differential temperature dependence to favor activation over diffusion.

Why Spike Anneal Matters

• Ultra-Shallow Junction Requirement: Sub-65nm transistors require source/drain junction depths < 20nm — conventional anneal temperatures cause boron and arsenic diffusion that pushes junctions too deep for acceptable short-channel control.
• Transistor Performance: Shallow junctions reduce short-channel effects, DIBL (Drain-Induced Barrier Lowering), and off-state leakage — spike anneal enables the junction depths that make FinFET and planar FET scaling viable.
• Dopant Activation: Even with minimal time at peak temperature, spike anneal achieves > 95% electrical activation of ion-implanted dopants, reducing parasitic source/drain series resistance.
• Damage Repair: Ion implantation creates crystal damage (amorphous regions, interstitials) that must be annealed; spike anneal heals implant damage while preserving shallow dopant profiles.
• Process Window: Spike anneal provides a narrow but usable process window between complete activation (requiring high T) and acceptable diffusion (requiring short t) — a window that narrows at each technology node.

Process Parameters

Temperature and Ramp Rates:

• Peak Temperature: 1000-1100°C for silicon; 600-800°C for germanium substrates.
• Ramp Rate: 50-250°C/second — limited by lamp power and wafer thermal mass.
• Cool Rate: 50-150°C/second — limited by wafer thermal mass and chamber wall design.
• Atmosphere: N₂ (inert) or forming gas; O₂ excluded to prevent uncontrolled oxide growth.

Evolution to Millisecond Annealing

Spike Anneal is the precision thermal scalpel of advanced transistor fabrication — achieving maximum dopant activation with minimum redistribution through the thermodynamic exploitation of differential Arrhenius kinetics, enabling the ultra-shallow junction depths that allow continued transistor scaling while maintaining the low series resistance essential for high-performance device operation.